Jump to content

Edit filter log

Details for log entry 22154237

08:07, 2 October 2018: 139.5.46.122 (talk) triggered filter 61, performing the action "edit" on Intel 8086. Actions taken: Tag; Filter description: New user removing references (examine | diff)

Changes made in edit

The has eight more or less general 16-bit [[processor register|registers]] (including the [[Stack-based memory allocation|stack pointer]] but excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as twice as many 8-bit registers (see figure) while the other four, SI, DI, BP, SP, are 16-bit only.
The has eight more or less general 16-bit [[processor register|registers]] (including the [[Stack-based memory allocation|stack pointer]] but excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as twice as many 8-bit registers (see figure) while the other four, SI, DI, BP, SP, are 16-bit only.


Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the ''destination'', while the other operand, the ''source'', can be either ''register'' or ''immediate''. A single memory location can also often be used as both ''source'' and ''destination'' which, among other factors, further contributes to a [[code density]] comparable to (and often better than) most eight-bit machines at the time.
Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the ''destination'', while the other operand, the ''source'', can be either ''register'' or ''immediate''. A single memory location can also often be used as both ''source'' and ''destination'' which, among other factors, further contributes to a [[code density]] comparable to (and often better than) most

The degree of generality of most registers are much greater than in the 8080 or 8085. However, 8086 registers were more specialized than in most contemporary [[minicomputer]]s and are also used implicitly by some instructions. While perfectly sensible for the assembly programmer, this makes register allocation for compilers more complicated compared to more orthogonal 16-bit and 32-bit processors of the time such as the [[PDP-11]], [[VAX]], [[68000]], [[32016]] etc. On the other hand, being more regular than the rather minimalistic but ubiquitous 8-bit microprocessors such as the [[MOS Technology 6502|6502]], [[Motorola 6800|6800]], [[6809]], [[Intel 8085|8085]], [[MCS-48]], [[Intel 8051|8051]], and other contemporary accumulator based machines, it is significantly easier to construct an efficient [[code generator]] for the 8086 architecture.

Another factor for this is that the 8086 also introduced some new instructions (not present in the 8080 and 8085) to better support stack-based high-level programming languages such as Pascal and [[PL/M]]; some of the more useful instructions are '''push''' ''mem-op'', and '''ret''' ''size'', supporting the "Pascal [[calling convention]]" directly. (Several others, such as '''push''' ''immed'' and '''enter''', were added in the subsequent 80186, 80286, and 80386 processors.)

A 64 KB (one segment) [[Stack (data structure)|stack]] growing towards lower addresses is supported in [[computer hardware|hardware]]; 16-bit words are pushed onto the stack, and the top of the stack is pointed to by SS:SP. There are 256 [[interrupt]]s, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the [[return address]]es.

The 8086 has 64 K of 8-bit (or alternatively 32 K of 16-bit word) [[I/O port]] space.


===Flags===
===Flags===
NUN
8086 has a 16-bit [[status register|flags register]]. Nine of these condition code flags are active, and indicate the current state of the processor: [[Carry flag]] (CF), [[Parity flag]] (PF), [[Auxiliary flag|Auxiliary carry flag]] (AF), [[Zero flag]] (ZF), [[Sign flag]] (SF), [[Trap flag]] (TF), [[IF (x86 flag)|Interrupt flag]] (IF), [[Direction flag]] (DF), and [[Overflow flag]] (OF).
Also referred to as the status word, the layout of the flags register is as follows:<ref>{{Cite book|url=https://www.worldcat.org/oclc/11091251|title=IAPX 86, 88, 186, and 188 user's manual : programmer's reference|others=Intel Corporation.|isbn=978-0835930352|location=Santa Clara, CA|oclc=11091251}}</ref>{{Rp|3-5}}
{| class="wikitable"
{| class="wikitable"
! Bit
! Bit

Action parameters

VariableValue
Whether or not the edit is marked as minor (no longer in use) (minor_edit)
false
Edit count of the user (user_editcount)
null
Name of the user account (user_name)
'139.5.46.122'
Age of the user account (user_age)
0
Groups (including implicit) the user is in (user_groups)
[ 0 => '*' ]
Rights that the user has (user_rights)
[ 0 => 'createaccount', 1 => 'read', 2 => 'edit', 3 => 'createtalk', 4 => 'writeapi', 5 => 'viewmywatchlist', 6 => 'editmywatchlist', 7 => 'viewmyprivateinfo', 8 => 'editmyprivateinfo', 9 => 'editmyoptions', 10 => 'abusefilter-log-detail', 11 => 'centralauth-merge', 12 => 'abusefilter-view', 13 => 'abusefilter-log', 14 => 'vipsscaler-test' ]
Whether the user is editing from mobile app (user_app)
false
Whether or not a user is editing through the mobile interface (user_mobile)
false
Page ID (page_id)
15063
Page namespace (page_namespace)
0
Page title without namespace (page_title)
'Intel 8086'
Full page title (page_prefixedtitle)
'Intel 8086'
Last ten users to contribute to the page (page_recent_contributors)
[ 0 => '157.33.201.64', 1 => '94.245.25.229', 2 => 'Vishal padme', 3 => '2601:54A:302:6BE0:A587:7EBA:EE94:250', 4 => '75.141.121.77', 5 => '2003:70:2F4F:2F01:33DE:395D:7C3F:C42F', 6 => 'Citation bot', 7 => 'Zi7ar21', 8 => 'Acc12345acc', 9 => 'Wtshymanski' ]
Page age in seconds (page_age)
537207542
Action (action)
'edit'
Edit summary/reason (summary)
'a+'
Old content model (old_content_model)
'wikitext'
New content model (new_content_model)
'wikitext'
Old page wikitext, before the edit (old_wikitext)
'{{Infobox CPU | name = Intel 8086 | image = Intel C8086.jpg | caption = The purple ceramic C8086 variant | produced-start = 1978 | produced-end = 1990s | slowest = 5 | slow-unit = MHz | fastest = 10 | fast-unit = MHz | manuf1 = [[Intel]], [[AMD]], [[NEC]], [[Fujitsu]], [[Harris Corporation|Harris]] ([[Intersil]]), [[Oki Electric Industry|OKI]], [[Siemens AG]], [[Texas Instruments]], [[Mitsubishi]], [[Panasonic]] (Matsushita) | arch = [[x86-16]] | pack1 = 40 pin [[Dual in-line package|DIP]] | predecessor = ([[Intel 8080]])<!-- not instruction set compatible --> | variant = [[Intel 8088|8088]] | successor = [[Intel 80186|80186]] and [[Intel 80286|80286]] (both of which were introduced in early 1982) | co-processor = [[X87#8087|Intel 8087]] | size-from = [[3 µm process|3&nbsp;µm]] | transistors-from = 29,000 }} The '''8086'''<ref>{{cite web |title=Microprocessor Hall of Fame |url=http://www.intel.com/museum/online/hist%5Fmicro/hof/ |publisher=Intel |accessdate=2007-08-11 |archiveurl=https://web.archive.org/web/20070706032836/http://www.intel.com/museum/online/hist_micro/hof/ |archivedate=2007-07-06 }}</ref> (also called '''iAPX 86''' )<ref name="i286">{{cite book|url=http://bitsavers.org/components/intel/80286/210498-001_iAPX_286_Programmers_Reference_1983.pdf|title=iAPX 286 Programmer's Reference|at=page 1-1|publisher=Intel|year=1983}}</ref> is a [[16-bit]] [[microprocessor]] chip designed by [[Intel]] between early 1976 and June 8, 1978, when it was released. The [[Intel 8088]], released July 1, 1979<ref>{{cite web|title=Happy Birthday, 8086: Limited-Edition 8th Gen Intel Core i7-8086K Delivers Top Gaming Experience |url=https://newsroom.intel.com/news/intel-i7-8086k-processor/|publisher=Intel}}</ref>, is a slightly modified chip with an external 8-bit [[Bus (computing)|data bus]] (allowing the use of cheaper and fewer supporting [[Integrated circuit|IC]]s<ref group="note" >Fewer TTL buffers, latches, multiplexers (although the amount of TTL <u>logic</u> was not drastically reduced). It also permits the use of cheap 8080-family ICs, where the 8254 CTC, [[Intel 8255|8255]] PIO, and 8259 PIC were used in the IBM PC design. In addition, it makes PCB layout simpler and boards cheaper, as well as demanding fewer (1- or 4-bit wide) DRAM chips.</ref>), and is notable as the processor used in the original [[IBM Personal Computer|IBM PC]] design, including the widespread version called [[IBM Personal Computer XT|IBM PC XT]]. The 8086 gave rise to the [[x86 architecture]], which eventually became Intel's most successful line of processors. On June 5th 2018, Intel released a limited edition CPU celebrating the anniversary of the Intel 8086, called the Intel Core i7-8086K.<ref>{{cite web|title=Happy Birthday, 8086: Limited-Edition 8th Gen Intel Core i7-8086K Delivers Top Gaming Experience |url=https://newsroom.intel.com/news/intel-i7-8086k-processor/|publisher=Intel}}</ref> ==History== ===Background=== In 1972, Intel launched the [[Intel 8008|8008]], the first 8-bit microprocessor.<ref group="note" >using enhancement load [[PMOS logic]] (requiring 14&nbsp;[[Volt|V]], achieving TTL compatibility by having V<sub>CC</sub> at +5&nbsp;V and V<sub>DD</sub> at −9&nbsp;V).</ref> It implemented an [[instruction set]] designed by [[Datapoint]] corporation with programmable [[Computer terminal|CRT terminals]] in mind, which also proved to be fairly general-purpose. The device needed several additional [[Integrated circuit|IC]]s to produce a functional computer, in part due to it being packaged in a small 18-pin "memory package", which ruled out the use of a separate address bus (Intel was primarily a [[DRAM]] manufacturer at the time). Two years later, Intel launched the [[Intel 8080|8080]],<ref group="note">Using non-saturated enhancement-load [[NMOS logic]] (demanding a higher gate voltage for the load-transistor gates).</ref> employing the new 40-pin [[Dual in-line package|DIL package]]s originally developed for [[calculator]] ICs to enable a separate address bus. It has an extended instruction set that is [[source-compatible]] (not [[binary compatible]]) with the 8008<ref >{{Cite web |website=CPU World |title=8080 family |url=http://www.cpu-world.com/CPUs/8080/ }}</ref> and also includes some [[16-bit]] instructions to make programming easier. The 8080 device, was eventually replaced by the [[Depletion-load NMOS logic|depletion-load]]-based [[Intel 8085|8085]] (1977), which sufficed with a single +5&nbsp;V power supply instead of the three different operating voltages of earlier chips.<ref group="note">Made possible with depletion-load nMOS logic (the 8085 was later made using HMOS processing, just like the 8086).</ref> Other well known 8-bit microprocessors that emerged during these years are [[Motorola 6800]] (1974), [[PIC microcontroller|General Instrument PIC16X]] (1975), [[MOS Technology 6502]] (1975), [[Zilog Z80]] (1976), and [[Motorola 6809]] (1978). ===The first x86 design=== [[File:Intel 8086 CPU Die.JPG|thumb|Intel 8086 CPU die image]] The 8086 project started in May 1976 and was originally intended as a temporary substitute for the ambitious and delayed [[iAPX 432]] project. It was an attempt to draw attention from the less-delayed 16- and 32-bit processors of other manufacturers (such as [[Motorola]], [[Zilog]], and [[National Semiconductor]]) and at the same time to counter the threat from the [[Zilog Z80]] (designed by former Intel employees), which became very successful. Both the architecture and the physical chip were therefore developed rather quickly by a small group of people, and using the same basic [[microarchitecture]] elements and physical implementation techniques as employed for the slightly older [[Intel 8085|8085]] (and for which the 8086 also would function as a continuation). Marketed as [[Source code compatibility|source compatible]], the 8086 was designed to allow [[assembly language]] for the 8008, 8080, or 8085 to be automatically converted into equivalent (suboptimal) 8086 source code, with little or no hand-editing. The programming model and instruction set is (loosely) based on the 8080 in order to make this possible. However, the 8086 design was expanded to support full 16-bit processing, instead of the fairly basic 8-bit capabilities of the 8080/8085. New kinds of instructions were added as well; full support for signed integers, base+offset addressing, and self-repeating operations were akin to the [[Z80]] design<ref>[http://www.pcworld.com/article/146957/birth_of_a_standard_the_intel_8086_microprocessor.html Birth of a Standard: The Intel 8086 Microprocessor. Thirty years ago, Intel released the 8086 processor, introducing the x86 architecture that underlies every PC — Windows, Mac, or Linux — produced today], PC World, June 17, 2008</ref> but were all made slightly more general in the 8086. Instructions directly supporting [[nested function|nested]] [[ALGOL]]-family languages such as [[Pascal (programming language)|Pascal]] and [[PL/M]] were also added. According to principal architect [[Stephen P. Morse]], this was a result of a more software-centric approach than in the design of earlier Intel processors (the designers had experience working with compiler implementations). Other enhancements included [[microcode]]d multiply and divide instructions and a bus structure better adapted to future coprocessors (such as [[Intel 8087|8087]] and [[Intel 8089|8089]]) and multiprocessor systems. The first revision of the instruction set and high level architecture was ready after about three months,<ref group="note" >Rev.0 of the instruction set and architecture was ready in about three months, according to Morse.</ref> and as almost no CAD tools were used, four engineers and 12&nbsp;layout people were simultaneously working on the chip.<ref group="note" >Using [[rubylith]], light boards, rulers, electric erasers, and a [[digitizer]] (according to Jenny Hernandez, member of the 8086 design team, in a statement made on Intel's webpage for its 25th birthday).</ref> The 8086 took a little more than two years from idea to working product, which was considered rather fast for a complex design in 1976–1978. The 8086 was sequenced<ref group="note" >8086 used less microcode than many competitors' designs, such as the MC68000 and others</ref> using a mixture of [[random logic]]<ref>Randall L. Geiger, Phillip E. Allen, Noel R. Strader ''VLSI design techniques for analog and digital circuits'', McGraw-Hill Book Co., 1990, {{ISBN|0-07-023253-9}}, page 779 "Random Logic vs. Structured Logic Forms", illustration of use of "random" describing CPU control logic</ref> and [[microcode]] and was implemented using depletion-load nMOS circuitry with approximately 20,000&nbsp;active [[transistor]]s (29,000 counting all [[Read only memory|ROM]] and [[Programmable logic array|PLA]] sites). It was soon moved to a new refined nMOS manufacturing process called [[HMOS]] (for High performance MOS) that Intel originally developed for manufacturing of fast [[static RAM]] products.<ref group="note" >Fast static RAMs in MOS technology (as fast as bipolar RAMs) was an important product for Intel during this period.</ref> This was followed by HMOS-II, HMOS-III versions, and, eventually, a fully static [[CMOS]] version for battery powered devices, manufactured using Intel's [[CHMOS]] processes.<ref group="note" >CHMOS is Intel's name for CMOS circuits manufactured using processing steps very similar to [[HMOS]].</ref> The original chip measured 33&nbsp;mm² and minimum feature size was 3.2&nbsp;μm. The architecture was defined by [[Stephen P. Morse]] with some help and assistance by Bruce Ravenel (the architect of the 8087) in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development team<ref group="note" >Other members of the design team were Peter A.Stoll and Jenny Hernandez.</ref> and Bill Pohlman the manager for the project. The legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers; the 8086 also lent its last two digits to later extended versions of the design, such as the [[Intel 286]] and the [[Intel 386]], all of which eventually became known as the [[x86]] family. (Another reference is that the [[PCI Configuration Space|PCI Vendor ID]] for Intel devices is 8086<sub>h</sub>.) ==Details== [[File:Intel 8086 pinout.svg|thumb|300px|The 8086 pin assignments in min and max mode]] ===Buses and operation=== All internal registers, as well as internal and external data buses, are 16&nbsp;bits wide, which firmly established the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus provides a 1&nbsp;[[Megabyte|MB]] physical address space (2<sup>20</sup> = 1,048,576). This address space is addressed by means of internal memory "segmentation". The data bus is [[multiplexed]] with the address bus in order to fit all of the control lines into a standard 40-pin [[dual in-line package]]. It provides a 16-bit I/O address bus, supporting 64&nbsp;[[Kilobyte|KB]] of separate I/O space. The maximum linear address space is limited to 64&nbsp;KB, simply because internal address/index registers are only 16&nbsp;bits wide. Programming over 64&nbsp;KB memory boundaries involves adjusting the segment registers (see below); this difficulty existed until the [[80386]] architecture introduced wider (32-bit) registers (the memory management hardware in the [[80286]] did not help in this regard, as its registers are still only 16 bits wide). ===Hardware modes=== Some of the control pins, which carry essential signals for all external operations, have more than one function depending upon whether the device is operated in ''min'' or ''max'' mode. The former mode is intended for small single-processor systems, while the latter is for medium or large systems using more than one processor (a kind of multiprocessor mode). Maximum mode is required when using a 8087 or 8089 coprocessor. The voltage on pin 33 (MN/{{overline|MX}}) determine the mode. Changing the state of pin 33 changes the function of certain other pins, most of which have to do with how the CPU handles the (local) bus. <ref group="note" >The IBM PC and PC/XT use an Intel 8088 running in maximum mode, which allows the CPU to work with an optional 8087 coprocessor installed in the math coprocessor socket on the PC or PC/XT mainboard. (The PC and PC/XT may require maximum mode for other reasons, such as perhaps to support the DMA controller.)</ref> The mode is usually hardwired into the circuit and therefore cannot be changed by software. The workings of these modes are described in terms of timing diagrams in Intel datasheets and manuals. In minimum mode, all control signals are generated by the 8086 itself. ===Registers and instructions=== {| class="infobox" style="font-size:75%;" |- |align="center" |''Intel 8086 registers'' |- | {| style="font-size:88%;" |- | style="width:10px; text-align:center;"| <sup>1</sup><sub>9</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>8</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>6</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub> | style="width:auto; background:white; color:black" | ''(bit position)'' |- |colspan="21" | '''Main registers''' <br> |- style="background:silver;color:black" | style="text-align:center; background:white" colspan="4"| &nbsp; | style="text-align:center;" colspan="8"| AH | style="text-align:center;" colspan="8"| AL | style="background:white; color:black;"| '''[[Accumulator (computing)|AX]]''' (primary accumulator) |- style="background:silver;color:black" | style="text-align:center; background:white" colspan="4"| &nbsp; | style="text-align:center;" colspan="8"| BH | style="text-align:center;" colspan="8"| BL | style="background:white; color:black;"| '''BX''' (base, accumulator) |- style="background:silver;color:black" | style="text-align:center; background:white" colspan="4"| &nbsp; | style="text-align:center;" colspan="8"| CH | style="text-align:center;" colspan="8"| CL | style="background:white; color:black;"| '''CX''' (counter, accumulator) |- style="background:silver;color:black" | style="text-align:center; background:white" colspan="4"| &nbsp; | style="text-align:center;" colspan="8"| DH | style="text-align:center;" colspan="8"| DL | style="background:white; color:black;"| '''DX''' (accumulator, extended acc.) |- |colspan="21" | '''Index registers''' <br> |- style="background:silver;color:black" | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="text-align:center;" colspan="16"| [[Index register|SI]] | style="background:white; color:black;"| '''S'''ource '''I'''ndex |- style="background:silver;color:black" | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="text-align:center;" colspan="16"| DI | style="background:white; color:black;"| '''D'''estination '''I'''ndex |- style="background:silver;color:black" | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="text-align:center;" colspan="16"| BP | style="background:white; color:black;"| '''B'''ase '''P'''ointer |- style="background:silver;color:black" | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="text-align:center;" colspan="16"| [[Stack register|SP]] | style="background:white; color:black;"| '''S'''tack '''P'''ointer |- |colspan="21" | '''Program counter''' <br> |- style="background:silver;color:black" | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="text-align:center;" colspan="16"| [[Program counter|IP]] | style="background:white; color:black;"| '''I'''nstruction '''P'''ointer |- |colspan="21" | '''Segment registers''' <br> |- style="background:silver;color:black" | style="text-align:center;" colspan="16"| CS | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="background:white; color:black;"| '''C'''ode '''S'''egment |- style="background:silver;color:black" | style="text-align:center;" colspan="16"| DS | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="background:white; color:black;"| '''D'''ata '''S'''egment |- style="background:silver;color:black" | style="text-align:center;" colspan="16"| ES | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="background:white; color:black;"| '''E'''xtra '''S'''egment |- style="background:silver;color:black" | style="text-align:center;" colspan="16"| SS | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="background:white; color:black;"| '''S'''tack '''S'''egment |- |colspan="21" | '''Status register''' |- style="background:silver;color:black" | style="text-align:center; background:white" colspan="4"| &nbsp; | style="text-align:center;"| - | style="text-align:center;"| - | style="text-align:center;"| - | style="text-align:center;"| - | style="text-align:center;"| [[Overflow flag|O]] | style="text-align:center;"| [[Direction flag|D]] | style="text-align:center;"| [[IF (x86 flag)|I]] | style="text-align:center;"| [[Trap flag|T]] | style="text-align:center;"| [[Sign flag|S]] | style="text-align:center;"| [[Zero flag|Z]] | style="text-align:center;"| - | style="text-align:center;"| [[Adjust flag|A]] | style="text-align:center;"| - | style="text-align:center;"| [[Parity flag|P]] | style="text-align:center;"| - | style="text-align:center;"| [[Carry flag|C]] | style="background:white; color:black" | Flags |} |} The has eight more or less general 16-bit [[processor register|registers]] (including the [[Stack-based memory allocation|stack pointer]] but excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as twice as many 8-bit registers (see figure) while the other four, SI, DI, BP, SP, are 16-bit only. Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the ''destination'', while the other operand, the ''source'', can be either ''register'' or ''immediate''. A single memory location can also often be used as both ''source'' and ''destination'' which, among other factors, further contributes to a [[code density]] comparable to (and often better than) most eight-bit machines at the time. The degree of generality of most registers are much greater than in the 8080 or 8085. However, 8086 registers were more specialized than in most contemporary [[minicomputer]]s and are also used implicitly by some instructions. While perfectly sensible for the assembly programmer, this makes register allocation for compilers more complicated compared to more orthogonal 16-bit and 32-bit processors of the time such as the [[PDP-11]], [[VAX]], [[68000]], [[32016]] etc. On the other hand, being more regular than the rather minimalistic but ubiquitous 8-bit microprocessors such as the [[MOS Technology 6502|6502]], [[Motorola 6800|6800]], [[6809]], [[Intel 8085|8085]], [[MCS-48]], [[Intel 8051|8051]], and other contemporary accumulator based machines, it is significantly easier to construct an efficient [[code generator]] for the 8086 architecture. Another factor for this is that the 8086 also introduced some new instructions (not present in the 8080 and 8085) to better support stack-based high-level programming languages such as Pascal and [[PL/M]]; some of the more useful instructions are '''push''' ''mem-op'', and '''ret''' ''size'', supporting the "Pascal [[calling convention]]" directly. (Several others, such as '''push'''&nbsp;''immed'' and '''enter''', were added in the subsequent 80186, 80286, and 80386 processors.) A 64&nbsp;KB (one segment) [[Stack (data structure)|stack]] growing towards lower addresses is supported in [[computer hardware|hardware]]; 16-bit words are pushed onto the stack, and the top of the stack is pointed to by SS:SP. There are 256&nbsp;[[interrupt]]s, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the [[return address]]es. The 8086 has 64&nbsp;K of 8-bit (or alternatively 32&nbsp;K of 16-bit word) [[I/O port]] space. ===Flags=== 8086 has a 16-bit [[status register|flags register]]. Nine of these condition code flags are active, and indicate the current state of the processor: [[Carry flag]] (CF), [[Parity flag]] (PF), [[Auxiliary flag|Auxiliary carry flag]] (AF), [[Zero flag]] (ZF), [[Sign flag]] (SF), [[Trap flag]] (TF), [[IF (x86 flag)|Interrupt flag]] (IF), [[Direction flag]] (DF), and [[Overflow flag]] (OF). Also referred to as the status word, the layout of the flags register is as follows:<ref>{{Cite book|url=https://www.worldcat.org/oclc/11091251|title=IAPX 86, 88, 186, and 188 user's manual : programmer's reference|others=Intel Corporation.|isbn=978-0835930352|location=Santa Clara, CA|oclc=11091251}}</ref>{{Rp|3-5}} {| class="wikitable" ! Bit | 15-12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |- ! Flag | &nbsp; | OF | DF | IF | TF | SF | ZF | &nbsp; | AF | &nbsp; | PF | &nbsp; | CF |} ===Segmentation=== {{See also|x86 memory segmentation}} There are also three 16-bit [[x86 memory segmentation|segment]] registers (see figure) that allow the 8086 [[Central processing unit|CPU]] to access one [[megabyte]] of memory in an unusual way. Rather than concatenating the segment register with the address register, as in most processors whose address space exceeds their register size, the 8086 shifts the 16-bit segment only four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, each external address can be referred to by 2<sup>12</sup> = 4096 different segment:offset pairs. {| style="margin-left:5em" |- | <tt>&nbsp; </tt><tt style="background:#DED">0110 1000 1000 0111</tt><tt>&nbsp;0000</tt> | '''Segment''', | 16 bits, shifted 4 bits left (or multiplied by 0x10) |- | <tt>+ &nbsp;&nbsp;&nbsp;&nbsp; </tt><tt style="background:#DDF">0011 0100 1010 1001</tt> | '''Offset''', | 16 bits |- style="text-decoration:line-through" | <tt>&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</tt> | |- | <tt>&nbsp; </tt><tt style="background:#FDF">0110 1011 1101 0001 1001</tt> | '''Address''', | 20 bits |} Although considered complicated and cumbersome by many programmers, this scheme also has advantages; a small program (less than 64&nbsp;KB) can be loaded starting at a fixed offset (such as 0000) in its own segment, avoiding the need for [[Relocation (computing)|relocation]], with at most 15&nbsp;bytes of alignment waste. Compilers for the 8086 family commonly support two types of [[pointer (computer programming)|pointer]], ''near'' and ''far''. Near pointers are 16-bit offsets implicitly associated with the program's code or data segment and so can be used only within parts of a program small enough to fit in one segment. Far pointers are 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also support ''huge'' pointers, which are like far pointers except that [[pointer arithmetic]] on a huge pointer treats it as a linear 20-bit pointer, while pointer arithmetic on a far pointer [[integer overflow|wraps around]] within its 16-bit offset without touching the segment part of the address. To avoid the need to specify ''near'' and ''far'' on numerous pointers, data structures, and functions, compilers also support "memory models" which specify default pointer sizes. The ''tiny'' (max 64K), ''small'' (max 128K), ''compact'' (data > 64K), ''medium'' (code > 64K), ''large'' (code,data > 64K), and ''huge'' (individual arrays > 64K) models cover practical combinations of near, far, and huge pointers for code and data. The ''tiny'' model means that code and data are shared in a single segment, just as in most 8-bit based processors, and can be used to build ''[[COM file|.com]]'' files for instance. Precompiled libraries often come in several versions compiled for different memory models. According to Morse et al.,.<ref name="File">[http://stevemorse.org/8086history/8086history.doc Intel Microprocessors : 8008 to 8086 by Stephen P. Morse et al.]</ref> the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16&nbsp;MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1&nbsp;MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low cost 40-pin package for the additional four address bus pins In principle, the address space of the x86 series ''could'' have been extended in later processors by increasing the shift value, as long as applications obtained their segments from the operating system and did not make assumptions about the equivalence of different segment:offset pairs.<ref group="note" >Some 80186 clones did change the shift value, but were never commonly used in desktop computers.</ref> In practice the use of "huge" pointers and similar mechanisms was widespread and the flat 32-bit addressing made possible with the 32-bit offset registers in the 80386 eventually extended the limited addressing range in a more general way (see below). Intel could have decided to implement memory in 16 bit words (which would have eliminated the {{overline|BHE}} signal along with much of the address bus complexities already described). This would mean that all instruction object codes and data would have to be accessed in 16-bit units. Users of the [[8080]] long ago realized, in hindsight, that the processor makes very efficient use of its memory. By having a large number of 8-bit object codes, the 8080 produces object code as compact as some of the most powerful minicomputers on the market at the time.<ref name="Osborne">Osborne 16 bit Processor Handbook (Adam Osborne & Gerry Kane) {{ISBN|0-931988-43-8}}</ref>{{rp|5–26}} If the 8086 is to retain 8-bit object codes and hence the efficient memory use of the 8080, then it cannot guarantee that (16-bit) opcodes and data will lie on an even-odd byte address boundary. The first 8-bit opcode will shift the next 8-bit instruction to an odd byte or a 16-bit instruction to an odd-even byte boundary. By implementing the {{overline|BHE}} signal and the extra logic needed, the 8086 allows instructions to exist as 1-byte, 3-byte or any other odd byte object codes.<ref name="Osborne"/>{{rp|5–26}} Simply put: this is a trade off. If memory addressing is simplified so that memory is only accessed in 16-bit units, memory will be used less efficiently. Intel decided to make the logic more complicated, but memory use more efficient. This was at a time when memory size was considerably smaller, and at a premium, than that which users are used to today.<ref name="Osborne"/>{{rp|5–26}} ====Porting older software==== Small programs could ignore the segmentation and just use plain 16-bit addressing. This allows [[8-bit]] software to be quite easily ported to the 8086. The authors of MS-DOS took advantage of this by providing an [[Application Programming Interface]] very similar to [[CP/M]] as well as including the simple ''.com'' executable file format, identical to CP/M. This was important when the 8086 and MS-DOS were new, because it allowed many existing CP/M (and other) applications to be quickly made available, greatly easing acceptance of the new platform. ===Example code=== The following 8086/8088 [[assembly language|assembler]] source code is for a subroutine named <code>_memcpy</code> that copies a block of data bytes of a given size from one location to another. The data block is copied one byte at a time, and the data movement and looping logic utilizes 16-bit operations. <!--NOTE: This is not intended to be optimized code, but to illustrate the variety of instructions available on the CPU--> <!--NOTE: The hex codes were assembled by hand, so there may be errors--> {| | <!--NOTE: DO NOT REMOVE BLANK LINES--><pre> 0000:1000 0000:1000 0000:1000 55 0000:1001 89 E5 0000:1003 06 0000:1004 8B 4E 06 0000:1007 E3 11 0000:1009 8B 76 04 0000:100C 8B 7E 02 0000:100F 1E 0000:1010 07 0000:1011 8A 04 0000:1013 88 05 0000:1015 46 0000:1016 47 0000:1017 49 0000:1018 75 F7 0000:101A 07 0000:101B 5D 0000:101C 29 C0 0000:101E C3 0000:101F </pre> | <source lang="nasm"> ; _memcpy(dst, src, len) ; Copy a block of memory from one location to another. ; ; Entry stack parameters ; [BP+6] = len, Number of bytes to copy ; [BP+4] = src, Address of source data block ; [BP+2] = dst, Address of target data block ; ; Return registers ; AX = Zero org 1000h ; Start at 0000:1000h _memcpy proc push bp ; Set up the call frame mov bp,sp push es ; Save ES mov cx,[bp+6] ; Set CX = len jcxz done ; If len = 0, return mov si,[bp+4] ; Set SI = src mov di,[bp+2] ; Set DI = dst push ds ; Set ES = DS pop es loop mov al,[si] ; Load AL from [src] mov [di],al ; Store AL to [dst] inc si ; Increment src inc di ; Increment dst dec cx ; Decrement len jnz loop ; Repeat the loop done pop es ; Restore ES pop bp ; Restore previous call frame sub ax,ax ; Set AX = 0 ret ; Return end proc </source> |} The code above uses the BP (base pointer) register to establish a [[call frame]], an area on the stack that contains all of the parameters and local variables for the execution of the subroutine. This kind of [[calling convention]] supports [[reentrancy (computing)|reentrant]] and [[recursion (computer science)|recursive]] code, and has been used by most ALGOL-like languages since the late 1950s. The above routine is a rather cumbersome way to copy blocks of data. The 8086 provides dedicated instructions for copying strings of bytes. These instructions assume that the source data is stored at DS:SI, the destination data is stored at ES:DI, and that the number of elements to copy is stored in CX. The above routine requires the source and the destination block to be in the same segment, therefore DS is copied to ES. The loop section of the above can be replaced by: {| | <pre> 0000:1011 FC 0000:1012 F2 0000:1013 A4 </pre> | <source lang=nasm> cld ; Copy towards higher addresses loop repnz ; Repeat until CX = 0 movsb ; Move the data block </source> |} This copies the block of data one byte at a time. The <code>REPNZ</code> instruction causes the following <code>MOVSB</code> to repeat until CX is zero, automatically incrementing SI and DI and decrementing CX as it repeats. Alternatively the <code>MOVSW</code> instruction can be used to copy 16-bit words (double bytes) at a time (in which case CX counts the number of words copied instead of the number of bytes). Most assemblers will properly recognize the <code>REPNZ</code> instruction if used as an in-line prefix to the <code>MOVSB</code> instruction, as in <code>REPNZ MOVSB</code>. This routine will operate correctly if interrupted, because the program counter will continue to point to the <code>REP</code> instruction until the block copy is completed. The copy will therefore continue from where it left off when the interrupt service routine returns control. ===Performance=== [[File:Intel 8086 block scheme.svg|thumb|405px|''Simplified block diagram over Intel 8088 (a variant of 8086); 1=main registers; 2=segment registers and IP; 3=address adder; 4=internal address bus; 5=instruction queue; 6=control unit (very simplified!); 7=bus interface; 8=internal databus; 9=ALU; 10/11/12=external address/data/control bus.'']] Although partly shadowed by other design choices in this particular chip, the [[multiplexed]] address and [[Bus (computing)|data buses]] limit performance slightly; transfers of 16-bit or 8-bit quantities are done in a four-clock memory access cycle, which is faster on 16-bit, although slower on 8-bit quantities, compared to many contemporary 8-bit based CPUs. As instructions vary from one to six bytes, fetch and execution are made [[Concurrency (computer science)|concurrent]] and decoupled into separate units (as it remains in today's x86 processors): The ''bus interface unit'' feeds the instruction stream to the ''execution unit'' through a 6-byte prefetch queue (a form of loosely coupled [[pipelining]]), speeding up operations on [[Processor register|register]]s and [[Operand|immediate]]s, while memory operations became slower (four years later, this performance problem was fixed with the [[80186]] and [[80286]]). However, the full (instead of partial) 16-bit architecture with a full width [[Arithmetic logic unit|ALU]] meant that 16-bit arithmetic instructions could now be performed with a single ALU cycle (instead of two, via internal carry, as in the 8080 and 8085), speeding up such instructions considerably. Combined with [[orthogonalization]]s of operations versus [[operand]] types and [[addressing mode]]s, as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below). {| class="wikitable" style="text-align: center; width: 100px; height: 50px;" |+ Execution times for typical instructions (in clock cycles)<ref>{{cite book|title=Microsoft Macro Assembler 5.0 Reference Manual|year=1987|publisher=Microsoft Corporation| quote=Timings and encodings in this manual are used with permission of Intel and come from the following publications: Intel Corporation. iAPX 86, 88, 186 and 188 User's Manual, Programmer's Reference, Santa Clara, Calif. 1986.|title-link=MASM}} (Similarly for iAPX 286, 80386, 80387.)</ref> |- style="vertical-align:bottom; border-bottom:3px double #999;" !align=left | instruction !align=left | register-register !align=left | register immediate !align=left | register-memory !align=left | memory-register !align=left | memory-immediate |- style="vertical-align:top; border-bottom:1px solid #999;" |mov || 2 || 4|| 8+EA || 9+EA || 10+EA |- style="vertical-align:top; border-bottom:1px solid #999;" |ALU || 3 ||4|| 9+EA, || 16+EA,|| 17+EA |- style="vertical-align:top; border-bottom:1px solid #999;" |jump || colspan="5" | ''register'' => 11 ; ''label'' => 15 ; ''condition,label'' => 16 |- style="vertical-align:top; border-bottom:1px solid #999;" |integer multiply || colspan="5" | 70~160 (depending on operand ''data'' as well as size) ''including'' any EA |- style="vertical-align:top; border-bottom:1px solid #999;" |integer divide || colspan="5" | 80~190 (depending on operand ''data'' as well as size) ''including'' any EA |} * EA = time to compute effective address, ranging from 5 to 12 cycles. * Timings are best case, depending on prefetch status, instruction alignment, and other factors. As can be seen from these tables, operations on registers and immediates were fast (between 2 and 4 cycles), while memory-operand instructions and jumps were quite slow; jumps took more cycles than on the simple [[Intel 8080|8080]] and [[Intel 8085|8085]], and the 8088 (used in the IBM PC) was additionally hampered by its narrower bus. The reasons why most memory related instructions were slow were threefold: * Loosely coupled fetch and execution units are efficient for instruction prefetch, but not for jumps and random data access (without special measures). * No dedicated address calculation adder was afforded; the microcode routines had to use the main ALU for this (although there was a dedicated ''segment'' + ''offset'' adder). * The address and data buses were [[multiplexing|multiplex]]ed, forcing a slightly longer (33~50%) bus cycle than in typical contemporary 8-bit processors. However, memory access performance was drastically enhanced with Intel's next generation of 8086 family CPUs. The [[Intel 80186|80186]] and [[Intel 80286|80286]] both had dedicated address calculation hardware, saving many cycles, and the 80286 also had separate (non-multiplexed) address and data buses. ===Floating point=== The 8086/8088 could be connected to a mathematical coprocessor to add hardware/microcode-based [[floating-point]] performance. The [[Intel 8087]] was the standard math coprocessor for the 8086 and 8088, operating on 80-bit numbers. Manufacturers like [[Cyrix]] (8087-compatible) and [[Weitek]] (''not'' 8087-compatible) eventually came up with high-performance floating-point coprocessors that competed with the 8087, as well as with the subsequent, higher-performing [[Intel 80387]]. ==Chip versions== The clock frequency was originally limited to 5&nbsp;MHz,<ref group="note" >(IBM PC used 4.77&nbsp;MHz, 4/3 the standard NTSC [[color burst]] frequency)</ref> but the last versions in [[HMOS]] were specified for 10&nbsp;MHz. HMOS-III and [[CMOS]] versions were manufactured for a long time (at least a while into the 1990s) for [[embedded system]]s, although its successor, the [[Intel 80186|80186]]/[[Intel 80188|80188]] (which includes some on-chip peripherals), has been more popular for embedded use. The 80C86, the CMOS version of the 8086, was used in the [[GRiDPad]], [[Toshiba T1200]], [[HP 110]], and finally the 1998–1999 [[Lunar Prospector]]. For the packaging, the Intel 8086 was available both in ceramic and plastic DIP packages. {| align="center" | [[Image:Intel_D8086_CS.jpg|thumb|A ceramic D8086 variant]] | [[Image:Intel_P8086.jpg|thumb|A plastic P8086 variant]] |} ===List of Intel 8086=== {| class="wikitable" |- ! Model number ! Frequency ! Technology ! Temperature range ! Date of release ! Price (USD){{ref|quantity}} |- | 8086 | 5&nbsp;MHz | HMOS | 0&nbsp;°C to 70&nbsp;°C<ref name="Intel Preview Special Issue 1980, page 29">8086 Available for industrial environment, Intel Preview Special Issue: 16-Bit Solutions, Intel Corporation, May/June 1980, page 29.</ref> | June 8, 1978<ref>[http://www.intel.com/pressroom/kits/quickrefyr.htm#1978 View Processors Chronologically by Date of Introduction:]</ref> | 86.65<ref>The 8086 Family: Concepts and realities, Intel Preview Special Issue: 16-Bit Solutions, Intel Corporation, May/June 1980, page 19.</ref> |- | 8086-1 | 10&nbsp;MHz | HMOS II | Commercial | | |- | 8086-2 | 8&nbsp;MHz | HMOS II | Commercial | May/June 1980<ref name="Intel Preview Special Issue 1980, page 17">New 8086 family products boost processor performance by 50 percent, Intel Preview Special Issue: 16-Bit Solutions, Intel Corporation, May/June 1980, page 17.</ref> | 200<ref name="Intel Preview Special Issue 1980, page 17"/> |- | 8086-4 | 4&nbsp;MHz | HMOS | Commercial | | |- | I8086 | | | −40&nbsp;°C to +85&nbsp;°C<ref name="Intel Preview Special Issue 1980, page 29"/> | May/June 1980<ref name="Intel Preview Special Issue 1980, page 29"/> | 173.25<ref name="Intel Preview Special Issue 1980, page 29"/> |} # {{note|quantity}} In quantity of 100. ===Derivatives and clones=== [[File:KL USSR KP1810BM86.jpg|thumb|Soviet clone [[K1810VM86]]]] [[File:Oki 80c86a.jpg|thumb|[[Oki Electric Industry|OKI]] M80C86A [[QFP|QFP-56]]]] [[File:UPD8086D-2 NEC 1984year 19week JAPAN.JPG|thumb|NEC μPD8086D-2 (8&nbsp;MHz) from the year 1984, week 19 JAPAN (clone of Intel D8086-2)]] Compatible—and, in many cases, enhanced—versions were manufactured by [[Fujitsu]], [[Harris Corporation|Harris]]/[[Intersil]], [[Oki Electric Industry|OKI]], [[Siemens AG]], [[Texas Instruments]], [[NEC]], [[Mitsubishi]], and [[AMD]]. For example, the [[NEC V20]] and [[NEC V30]] pair were hardware-compatible with the 8088 and 8086 even though NEC made original Intel clones μPD8088D and μPD8086D respectively, but incorporated the instruction set of the 80186 along with some (but not all) of the 80186 speed enhancements, providing a drop-in capability to upgrade both instruction set and processing speed without manufacturers having to modify their designs. Such relatively simple and low-power 8086-compatible processors in CMOS are still used in embedded systems. The electronics industry of the [[Soviet Union]] was able to replicate the 8086 through {{citation needed-span|both [[industrial espionage]] and reverse engineering|date=October 2013}}. The resulting chip, [[K1810VM86]], was binary and pin-compatible with the 8086. i8086 and i8088 were respectively the cores of the Soviet-made PC-compatible [[EC1831]] and [[EC1832]] desktops. (EC1831 is the EC identification of IZOT 1036C and EC1832 is the EC identification of IZOT 1037C, developed and manufactured in Bulgaria. EC stands for Единая Система.) However, the EC1831 computer (IZOT 1036C) had significant hardware differences from the IBM PC prototype. The EC1831 was the first PC-compatible computer with dynamic bus sizing (US Pat. No 4,831,514). Later some of the EC1831 principles were adopted in PS/2 (US Pat. No 5,548,786) and some other machines (UK Patent Application, Publication No. GB-A-2211325, Published June 28, 1989). ==Support chips== * [[Intel 8237]]: direct memory access (DMA) controller * [[Intel 8251]]: universal synchronous/asynchronous receiver/transmitter at 19.2 kbit/s * [[Intel 8253]]: programmable interval timer, 3x 16-bit max 10&nbsp;MHz * [[Intel 8255]]: programmable peripheral interface, 3x 8-bit I/O pins used for printer connection etc. * [[Intel 8259]]: programmable interrupt controller * [[Intel 8279]]: keyboard/display controller, scans a keyboard matrix and display matrix like [[Seven-segment display|7-seg]] * [[Intel 8282]]/[[Intel 8283|8283]]: 8-bit latch * [[Intel 8284]]: clock generator * [[Intel 8286]]/[[Intel 8287|8287]]: bidirectional 8-bit driver. In 1980 both Intel I8286/I8287 (industrial grade) version were available for 16.25 USD in quantities of 100.<ref name="Intel Preview Special Issue 1980, page 29"/> * [[Intel 8288]]: bus controller * [[Intel 8289]]: bus arbiter * [[Floppy-disk controller|NEC µPD765 or Intel 8272A]]: floppy controller<!--also NE72065--><ref>{{cite web|title=The floppy controller evolution &#124; OS/2 Museum |date=2011-05-26 |accessdate=2016-05-12 |url=http://www.os2museum.com/wp/the-floppy-controller-evolution/ |quote=In the original IBM PC (1981) and PC/XT (1983), the FDC was physically located on a separate diskette adapter card. The FDC itself was a NEC µPD765A or a compatible part, such as the Intel 8272A.}}</ref> ==Microcomputers using the 8086== * The Intel [[Multibus]]-compatible [[single-board computer]] ISBC 86/12 was announced in 1978.<ref>{{cite journal | title = Intel Adds 16-Bit Single Board | journal = Computerworld | date = December 11, 1978 | pages = 86 | volume = XII | issue = 50 | issn = 0010-4841 | url = https://books.google.com/books?id=07X0ovA_MmEC&pg=PA86#v=onepage&q&f=false | last1 = Enterprise | first1 = I.D.G }}</ref> * The [[Xerox NoteTaker]] was one of the earliest [[portable computer]] designs in 1978 and used three 8086 chips (as CPU, graphics processor, and I/O processor), but never entered commercial production. * [[Seattle Computer Products]] shipped [[S-100 bus]] based 8086 systems (SCP200B) as early as November 1979. * The Norwegian [[Mycron]] 2000, introduced in 1980. * One of the most influential microcomputers of all, the [[IBM PC]], used the [[Intel 8088]], a version of the 8086 with an 8-bit [[Bus (computing)|data bus]] (as mentioned above). * The first [[Compaq Deskpro]] used an 8086 running at 7.16&nbsp;MHz, but was compatible with add-in cards designed for the 4.77&nbsp;MHz [[IBM PC XT]] and could switch the CPU down to the lower speed (which also switched in a memory bus buffer to simulate the 8088's slower access) to avoid software timing issues. * An 8&nbsp;MHz 8086-2 was used in the [[Olivetti M24|AT&T 6300 PC]] (built by [[Olivetti]], and known globally under several brands and model numbers), an IBM PC-compatible desktop microcomputer. The M24 / PC 6300 has IBM PC/XT compatible 8-bit expansion slots, but some of them have a proprietary extension providing the full 16-bit data bus of the 8086 CPU (similar in concept to the 16-bit slots of the [[IBM PC AT]], but different in the design details, and physically incompatible), and all system peripherals including the onboard video system also enjoy 16-bit data transfers. The later Olivetti M24SP featured an 8086-2 running at the full maximum 10&nbsp;MHz. * The [[IBM Personal System/2|IBM PS/2]] models 25 and 30 were built with an 8&nbsp;MHz 8086. * The Amstrad/Schneider [[Amstrad PC1512|PC1512]], [[Amstrad PC1640|PC1640]], [[Amstrad PC2086|PC2086]], [[Amstrad PC3086|PC3086]] and [[Amstrad PC5086|PC5086]] all used 8086 CPUs at 8&nbsp;MHz. * The [[NEC PC-9801]]. * The [[Tandy 1000]] SL-series and RL machines used 9.47&nbsp;MHz 8086 CPUs. * The [[IBM Displaywriter]] word processing machine<ref name = "InfoWorld Aug 1982" >{{cite journal | last = Zachmann | first = Mark | title = Flaws in IBM Personal Computer frustrate critic | journal = InfoWorld | volume = 4 | issue = 33 | pages =57–58 | date = August 23, 1982 | url = https://books.google.com/books?id=VDAEAAAAMBAJ&pg=PA57| issn = 0199-6649 | quote = the IBM Displaywriter is noticeably more expensive than other industrial micros that use the 8086. }}</ref> and the Wang Professional Computer, manufactured by [[Wang Laboratories]], also used the 8086. * [[NASA]] used original 8086 CPUs on equipment for ground-based maintenance of the [[Space Shuttle Discovery]] until the end of the space shuttle program in 2011. This decision was made to prevent [[software regression]] that might result from upgrading or from switching to imperfect clones.<ref>[https://www.nytimes.com/2002/05/12/technology/ebusiness/12NASA.html?pagewanted=2 For Old Parts, NASA Boldly Goes ... on eBay], May 12, 2002.</ref> * KAMAN Process and Area Radiation Monitors<ref>Kaman Tech. Manual</ref> ==See also== * [[Transistor count]] * [[iAPX]], for the iAPX name ==Notes== {{Reflist|group=note|2}} ==References== {{Reflist|35em}} ==External links== {{Commons category}} * [http://datasheets.chipdb.org/Intel/x86/808x/datashts/8086 Intel datasheets] * [http://www.cpu-world.com/CPUs/8086/ List of 8086 CPUs and their clones at CPUworld.com] * [http://www.cpu-world.com/info/Pinouts/8086.html 8086 Pinouts] * [http://www.8085projects.info/post/Maximum-Mode-Interface.aspx Maximum Mode Interface] * [http://matthieu.benoit.free.fr/cross/data_sheets/Intel_8086_users_manual.htm The 8086 User's manual October 1979 INTEL Corporation] ([[PDF]] document) * [http://www.shubhsblog.com/category/8086-programs/ 8086 program codes using emu8086 (Version 4.08) Emulator] * [http://sourceforge.net/p/fake86/code/ci/master/tree/src/fake86/cpu.c Intel 8086/80186 emulator written in C, this file is part of a larger PC emulator] {{Intel processors|discontinued}} {{Authority control}} [[Category:Computer-related introductions in 1978]] [[Category:Intel x86 microprocessors|80086]]<!--Note: NOT a typo for 8086, this is done for numberical ordering of categories-->'
New page wikitext, after the edit (new_wikitext)
'{{Infobox CPU | name = Intel 8086 | image = Intel C8086.jpg | caption = The purple ceramic C8086 variant | produced-start = 1978 | produced-end = 1990s | slowest = 5 | slow-unit = MHz | fastest = 10 | fast-unit = MHz | manuf1 = [[Intel]], [[AMD]], [[NEC]], [[Fujitsu]], [[Harris Corporation|Harris]] ([[Intersil]]), [[Oki Electric Industry|OKI]], [[Siemens AG]], [[Texas Instruments]], [[Mitsubishi]], [[Panasonic]] (Matsushita) | arch = [[x86-16]] | pack1 = 40 pin [[Dual in-line package|DIP]] | predecessor = ([[Intel 8080]])<!-- not instruction set compatible --> | variant = [[Intel 8088|8088]] | successor = [[Intel 80186|80186]] and [[Intel 80286|80286]] (both of which were introduced in early 1982) | co-processor = [[X87#8087|Intel 8087]] | size-from = [[3 µm process|3&nbsp;µm]] | transistors-from = 29,000 }} The '''8086'''<ref>{{cite web |title=Microprocessor Hall of Fame |url=http://www.intel.com/museum/online/hist%5Fmicro/hof/ |publisher=Intel |accessdate=2007-08-11 |archiveurl=https://web.archive.org/web/20070706032836/http://www.intel.com/museum/online/hist_micro/hof/ |archivedate=2007-07-06 }}</ref> (also called '''iAPX 86''' )<ref name="i286">{{cite book|url=http://bitsavers.org/components/intel/80286/210498-001_iAPX_286_Programmers_Reference_1983.pdf|title=iAPX 286 Programmer's Reference|at=page 1-1|publisher=Intel|year=1983}}</ref> is a [[16-bit]] [[microprocessor]] chip designed by [[Intel]] between early 1976 and June 8, 1978, when it was released. The [[Intel 8088]], released July 1, 1979<ref>{{cite web|title=Happy Birthday, 8086: Limited-Edition 8th Gen Intel Core i7-8086K Delivers Top Gaming Experience |url=https://newsroom.intel.com/news/intel-i7-8086k-processor/|publisher=Intel}}</ref>, is a slightly modified chip with an external 8-bit [[Bus (computing)|data bus]] (allowing the use of cheaper and fewer supporting [[Integrated circuit|IC]]s<ref group="note" >Fewer TTL buffers, latches, multiplexers (although the amount of TTL <u>logic</u> was not drastically reduced). It also permits the use of cheap 8080-family ICs, where the 8254 CTC, [[Intel 8255|8255]] PIO, and 8259 PIC were used in the IBM PC design. In addition, it makes PCB layout simpler and boards cheaper, as well as demanding fewer (1- or 4-bit wide) DRAM chips.</ref>), and is notable as the processor used in the original [[IBM Personal Computer|IBM PC]] design, including the widespread version called [[IBM Personal Computer XT|IBM PC XT]]. The 8086 gave rise to the [[x86 architecture]], which eventually became Intel's most successful line of processors. On June 5th 2018, Intel released a limited edition CPU celebrating the anniversary of the Intel 8086, called the Intel Core i7-8086K.<ref>{{cite web|title=Happy Birthday, 8086: Limited-Edition 8th Gen Intel Core i7-8086K Delivers Top Gaming Experience |url=https://newsroom.intel.com/news/intel-i7-8086k-processor/|publisher=Intel}}</ref> ==History== ===Background=== In 1972, Intel launched the [[Intel 8008|8008]], the first 8-bit microprocessor.<ref group="note" >using enhancement load [[PMOS logic]] (requiring 14&nbsp;[[Volt|V]], achieving TTL compatibility by having V<sub>CC</sub> at +5&nbsp;V and V<sub>DD</sub> at −9&nbsp;V).</ref> It implemented an [[instruction set]] designed by [[Datapoint]] corporation with programmable [[Computer terminal|CRT terminals]] in mind, which also proved to be fairly general-purpose. The device needed several additional [[Integrated circuit|IC]]s to produce a functional computer, in part due to it being packaged in a small 18-pin "memory package", which ruled out the use of a separate address bus (Intel was primarily a [[DRAM]] manufacturer at the time). Two years later, Intel launched the [[Intel 8080|8080]],<ref group="note">Using non-saturated enhancement-load [[NMOS logic]] (demanding a higher gate voltage for the load-transistor gates).</ref> employing the new 40-pin [[Dual in-line package|DIL package]]s originally developed for [[calculator]] ICs to enable a separate address bus. It has an extended instruction set that is [[source-compatible]] (not [[binary compatible]]) with the 8008<ref >{{Cite web |website=CPU World |title=8080 family |url=http://www.cpu-world.com/CPUs/8080/ }}</ref> and also includes some [[16-bit]] instructions to make programming easier. The 8080 device, was eventually replaced by the [[Depletion-load NMOS logic|depletion-load]]-based [[Intel 8085|8085]] (1977), which sufficed with a single +5&nbsp;V power supply instead of the three different operating voltages of earlier chips.<ref group="note">Made possible with depletion-load nMOS logic (the 8085 was later made using HMOS processing, just like the 8086).</ref> Other well known 8-bit microprocessors that emerged during these years are [[Motorola 6800]] (1974), [[PIC microcontroller|General Instrument PIC16X]] (1975), [[MOS Technology 6502]] (1975), [[Zilog Z80]] (1976), and [[Motorola 6809]] (1978). ===The first x86 design=== [[File:Intel 8086 CPU Die.JPG|thumb|Intel 8086 CPU die image]] The 8086 project started in May 1976 and was originally intended as a temporary substitute for the ambitious and delayed [[iAPX 432]] project. It was an attempt to draw attention from the less-delayed 16- and 32-bit processors of other manufacturers (such as [[Motorola]], [[Zilog]], and [[National Semiconductor]]) and at the same time to counter the threat from the [[Zilog Z80]] (designed by former Intel employees), which became very successful. Both the architecture and the physical chip were therefore developed rather quickly by a small group of people, and using the same basic [[microarchitecture]] elements and physical implementation techniques as employed for the slightly older [[Intel 8085|8085]] (and for which the 8086 also would function as a continuation). Marketed as [[Source code compatibility|source compatible]], the 8086 was designed to allow [[assembly language]] for the 8008, 8080, or 8085 to be automatically converted into equivalent (suboptimal) 8086 source code, with little or no hand-editing. The programming model and instruction set is (loosely) based on the 8080 in order to make this possible. However, the 8086 design was expanded to support full 16-bit processing, instead of the fairly basic 8-bit capabilities of the 8080/8085. New kinds of instructions were added as well; full support for signed integers, base+offset addressing, and self-repeating operations were akin to the [[Z80]] design<ref>[http://www.pcworld.com/article/146957/birth_of_a_standard_the_intel_8086_microprocessor.html Birth of a Standard: The Intel 8086 Microprocessor. Thirty years ago, Intel released the 8086 processor, introducing the x86 architecture that underlies every PC — Windows, Mac, or Linux — produced today], PC World, June 17, 2008</ref> but were all made slightly more general in the 8086. Instructions directly supporting [[nested function|nested]] [[ALGOL]]-family languages such as [[Pascal (programming language)|Pascal]] and [[PL/M]] were also added. According to principal architect [[Stephen P. Morse]], this was a result of a more software-centric approach than in the design of earlier Intel processors (the designers had experience working with compiler implementations). Other enhancements included [[microcode]]d multiply and divide instructions and a bus structure better adapted to future coprocessors (such as [[Intel 8087|8087]] and [[Intel 8089|8089]]) and multiprocessor systems. The first revision of the instruction set and high level architecture was ready after about three months,<ref group="note" >Rev.0 of the instruction set and architecture was ready in about three months, according to Morse.</ref> and as almost no CAD tools were used, four engineers and 12&nbsp;layout people were simultaneously working on the chip.<ref group="note" >Using [[rubylith]], light boards, rulers, electric erasers, and a [[digitizer]] (according to Jenny Hernandez, member of the 8086 design team, in a statement made on Intel's webpage for its 25th birthday).</ref> The 8086 took a little more than two years from idea to working product, which was considered rather fast for a complex design in 1976–1978. The 8086 was sequenced<ref group="note" >8086 used less microcode than many competitors' designs, such as the MC68000 and others</ref> using a mixture of [[random logic]]<ref>Randall L. Geiger, Phillip E. Allen, Noel R. Strader ''VLSI design techniques for analog and digital circuits'', McGraw-Hill Book Co., 1990, {{ISBN|0-07-023253-9}}, page 779 "Random Logic vs. Structured Logic Forms", illustration of use of "random" describing CPU control logic</ref> and [[microcode]] and was implemented using depletion-load nMOS circuitry with approximately 20,000&nbsp;active [[transistor]]s (29,000 counting all [[Read only memory|ROM]] and [[Programmable logic array|PLA]] sites). It was soon moved to a new refined nMOS manufacturing process called [[HMOS]] (for High performance MOS) that Intel originally developed for manufacturing of fast [[static RAM]] products.<ref group="note" >Fast static RAMs in MOS technology (as fast as bipolar RAMs) was an important product for Intel during this period.</ref> This was followed by HMOS-II, HMOS-III versions, and, eventually, a fully static [[CMOS]] version for battery powered devices, manufactured using Intel's [[CHMOS]] processes.<ref group="note" >CHMOS is Intel's name for CMOS circuits manufactured using processing steps very similar to [[HMOS]].</ref> The original chip measured 33&nbsp;mm² and minimum feature size was 3.2&nbsp;μm. The architecture was defined by [[Stephen P. Morse]] with some help and assistance by Bruce Ravenel (the architect of the 8087) in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development team<ref group="note" >Other members of the design team were Peter A.Stoll and Jenny Hernandez.</ref> and Bill Pohlman the manager for the project. The legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers; the 8086 also lent its last two digits to later extended versions of the design, such as the [[Intel 286]] and the [[Intel 386]], all of which eventually became known as the [[x86]] family. (Another reference is that the [[PCI Configuration Space|PCI Vendor ID]] for Intel devices is 8086<sub>h</sub>.) ==Details== [[File:Intel 8086 pinout.svg|thumb|300px|The 8086 pin assignments in min and max mode]] ===Buses and operation=== All internal registers, as well as internal and external data buses, are 16&nbsp;bits wide, which firmly established the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus provides a 1&nbsp;[[Megabyte|MB]] physical address space (2<sup>20</sup> = 1,048,576). This address space is addressed by means of internal memory "segmentation". The data bus is [[multiplexed]] with the address bus in order to fit all of the control lines into a standard 40-pin [[dual in-line package]]. It provides a 16-bit I/O address bus, supporting 64&nbsp;[[Kilobyte|KB]] of separate I/O space. The maximum linear address space is limited to 64&nbsp;KB, simply because internal address/index registers are only 16&nbsp;bits wide. Programming over 64&nbsp;KB memory boundaries involves adjusting the segment registers (see below); this difficulty existed until the [[80386]] architecture introduced wider (32-bit) registers (the memory management hardware in the [[80286]] did not help in this regard, as its registers are still only 16 bits wide). ===Hardware modes=== Some of the control pins, which carry essential signals for all external operations, have more than one function depending upon whether the device is operated in ''min'' or ''max'' mode. The former mode is intended for small single-processor systems, while the latter is for medium or large systems using more than one processor (a kind of multiprocessor mode). Maximum mode is required when using a 8087 or 8089 coprocessor. The voltage on pin 33 (MN/{{overline|MX}}) determine the mode. Changing the state of pin 33 changes the function of certain other pins, most of which have to do with how the CPU handles the (local) bus. <ref group="note" >The IBM PC and PC/XT use an Intel 8088 running in maximum mode, which allows the CPU to work with an optional 8087 coprocessor installed in the math coprocessor socket on the PC or PC/XT mainboard. (The PC and PC/XT may require maximum mode for other reasons, such as perhaps to support the DMA controller.)</ref> The mode is usually hardwired into the circuit and therefore cannot be changed by software. The workings of these modes are described in terms of timing diagrams in Intel datasheets and manuals. In minimum mode, all control signals are generated by the 8086 itself. ===Registers and instructions=== {| class="infobox" style="font-size:75%;" |- |align="center" |''Intel 8086 registers'' |- | {| style="font-size:88%;" |- | style="width:10px; text-align:center;"| <sup>1</sup><sub>9</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>8</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>6</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub> | style="width:auto; background:white; color:black" | ''(bit position)'' |- |colspan="21" | '''Main registers''' <br> |- style="background:silver;color:black" | style="text-align:center; background:white" colspan="4"| &nbsp; | style="text-align:center;" colspan="8"| AH | style="text-align:center;" colspan="8"| AL | style="background:white; color:black;"| '''[[Accumulator (computing)|AX]]''' (primary accumulator) |- style="background:silver;color:black" | style="text-align:center; background:white" colspan="4"| &nbsp; | style="text-align:center;" colspan="8"| BH | style="text-align:center;" colspan="8"| BL | style="background:white; color:black;"| '''BX''' (base, accumulator) |- style="background:silver;color:black" | style="text-align:center; background:white" colspan="4"| &nbsp; | style="text-align:center;" colspan="8"| CH | style="text-align:center;" colspan="8"| CL | style="background:white; color:black;"| '''CX''' (counter, accumulator) |- style="background:silver;color:black" | style="text-align:center; background:white" colspan="4"| &nbsp; | style="text-align:center;" colspan="8"| DH | style="text-align:center;" colspan="8"| DL | style="background:white; color:black;"| '''DX''' (accumulator, extended acc.) |- |colspan="21" | '''Index registers''' <br> |- style="background:silver;color:black" | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="text-align:center;" colspan="16"| [[Index register|SI]] | style="background:white; color:black;"| '''S'''ource '''I'''ndex |- style="background:silver;color:black" | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="text-align:center;" colspan="16"| DI | style="background:white; color:black;"| '''D'''estination '''I'''ndex |- style="background:silver;color:black" | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="text-align:center;" colspan="16"| BP | style="background:white; color:black;"| '''B'''ase '''P'''ointer |- style="background:silver;color:black" | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="text-align:center;" colspan="16"| [[Stack register|SP]] | style="background:white; color:black;"| '''S'''tack '''P'''ointer |- |colspan="21" | '''Program counter''' <br> |- style="background:silver;color:black" | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="text-align:center;" colspan="16"| [[Program counter|IP]] | style="background:white; color:black;"| '''I'''nstruction '''P'''ointer |- |colspan="21" | '''Segment registers''' <br> |- style="background:silver;color:black" | style="text-align:center;" colspan="16"| CS | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="background:white; color:black;"| '''C'''ode '''S'''egment |- style="background:silver;color:black" | style="text-align:center;" colspan="16"| DS | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="background:white; color:black;"| '''D'''ata '''S'''egment |- style="background:silver;color:black" | style="text-align:center;" colspan="16"| ES | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="background:white; color:black;"| '''E'''xtra '''S'''egment |- style="background:silver;color:black" | style="text-align:center;" colspan="16"| SS | style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0 | style="background:white; color:black;"| '''S'''tack '''S'''egment |- |colspan="21" | '''Status register''' |- style="background:silver;color:black" | style="text-align:center; background:white" colspan="4"| &nbsp; | style="text-align:center;"| - | style="text-align:center;"| - | style="text-align:center;"| - | style="text-align:center;"| - | style="text-align:center;"| [[Overflow flag|O]] | style="text-align:center;"| [[Direction flag|D]] | style="text-align:center;"| [[IF (x86 flag)|I]] | style="text-align:center;"| [[Trap flag|T]] | style="text-align:center;"| [[Sign flag|S]] | style="text-align:center;"| [[Zero flag|Z]] | style="text-align:center;"| - | style="text-align:center;"| [[Adjust flag|A]] | style="text-align:center;"| - | style="text-align:center;"| [[Parity flag|P]] | style="text-align:center;"| - | style="text-align:center;"| [[Carry flag|C]] | style="background:white; color:black" | Flags |} |} The has eight more or less general 16-bit [[processor register|registers]] (including the [[Stack-based memory allocation|stack pointer]] but excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as twice as many 8-bit registers (see figure) while the other four, SI, DI, BP, SP, are 16-bit only. Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the ''destination'', while the other operand, the ''source'', can be either ''register'' or ''immediate''. A single memory location can also often be used as both ''source'' and ''destination'' which, among other factors, further contributes to a [[code density]] comparable to (and often better than) most ===Flags=== NUN {| class="wikitable" ! Bit | 15-12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |- ! Flag | &nbsp; | OF | DF | IF | TF | SF | ZF | &nbsp; | AF | &nbsp; | PF | &nbsp; | CF |} ===Segmentation=== {{See also|x86 memory segmentation}} There are also three 16-bit [[x86 memory segmentation|segment]] registers (see figure) that allow the 8086 [[Central processing unit|CPU]] to access one [[megabyte]] of memory in an unusual way. Rather than concatenating the segment register with the address register, as in most processors whose address space exceeds their register size, the 8086 shifts the 16-bit segment only four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, each external address can be referred to by 2<sup>12</sup> = 4096 different segment:offset pairs. {| style="margin-left:5em" |- | <tt>&nbsp; </tt><tt style="background:#DED">0110 1000 1000 0111</tt><tt>&nbsp;0000</tt> | '''Segment''', | 16 bits, shifted 4 bits left (or multiplied by 0x10) |- | <tt>+ &nbsp;&nbsp;&nbsp;&nbsp; </tt><tt style="background:#DDF">0011 0100 1010 1001</tt> | '''Offset''', | 16 bits |- style="text-decoration:line-through" | <tt>&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</tt> | |- | <tt>&nbsp; </tt><tt style="background:#FDF">0110 1011 1101 0001 1001</tt> | '''Address''', | 20 bits |} Although considered complicated and cumbersome by many programmers, this scheme also has advantages; a small program (less than 64&nbsp;KB) can be loaded starting at a fixed offset (such as 0000) in its own segment, avoiding the need for [[Relocation (computing)|relocation]], with at most 15&nbsp;bytes of alignment waste. Compilers for the 8086 family commonly support two types of [[pointer (computer programming)|pointer]], ''near'' and ''far''. Near pointers are 16-bit offsets implicitly associated with the program's code or data segment and so can be used only within parts of a program small enough to fit in one segment. Far pointers are 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also support ''huge'' pointers, which are like far pointers except that [[pointer arithmetic]] on a huge pointer treats it as a linear 20-bit pointer, while pointer arithmetic on a far pointer [[integer overflow|wraps around]] within its 16-bit offset without touching the segment part of the address. To avoid the need to specify ''near'' and ''far'' on numerous pointers, data structures, and functions, compilers also support "memory models" which specify default pointer sizes. The ''tiny'' (max 64K), ''small'' (max 128K), ''compact'' (data > 64K), ''medium'' (code > 64K), ''large'' (code,data > 64K), and ''huge'' (individual arrays > 64K) models cover practical combinations of near, far, and huge pointers for code and data. The ''tiny'' model means that code and data are shared in a single segment, just as in most 8-bit based processors, and can be used to build ''[[COM file|.com]]'' files for instance. Precompiled libraries often come in several versions compiled for different memory models. According to Morse et al.,.<ref name="File">[http://stevemorse.org/8086history/8086history.doc Intel Microprocessors : 8008 to 8086 by Stephen P. Morse et al.]</ref> the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16&nbsp;MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1&nbsp;MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low cost 40-pin package for the additional four address bus pins In principle, the address space of the x86 series ''could'' have been extended in later processors by increasing the shift value, as long as applications obtained their segments from the operating system and did not make assumptions about the equivalence of different segment:offset pairs.<ref group="note" >Some 80186 clones did change the shift value, but were never commonly used in desktop computers.</ref> In practice the use of "huge" pointers and similar mechanisms was widespread and the flat 32-bit addressing made possible with the 32-bit offset registers in the 80386 eventually extended the limited addressing range in a more general way (see below). Intel could have decided to implement memory in 16 bit words (which would have eliminated the {{overline|BHE}} signal along with much of the address bus complexities already described). This would mean that all instruction object codes and data would have to be accessed in 16-bit units. Users of the [[8080]] long ago realized, in hindsight, that the processor makes very efficient use of its memory. By having a large number of 8-bit object codes, the 8080 produces object code as compact as some of the most powerful minicomputers on the market at the time.<ref name="Osborne">Osborne 16 bit Processor Handbook (Adam Osborne & Gerry Kane) {{ISBN|0-931988-43-8}}</ref>{{rp|5–26}} If the 8086 is to retain 8-bit object codes and hence the efficient memory use of the 8080, then it cannot guarantee that (16-bit) opcodes and data will lie on an even-odd byte address boundary. The first 8-bit opcode will shift the next 8-bit instruction to an odd byte or a 16-bit instruction to an odd-even byte boundary. By implementing the {{overline|BHE}} signal and the extra logic needed, the 8086 allows instructions to exist as 1-byte, 3-byte or any other odd byte object codes.<ref name="Osborne"/>{{rp|5–26}} Simply put: this is a trade off. If memory addressing is simplified so that memory is only accessed in 16-bit units, memory will be used less efficiently. Intel decided to make the logic more complicated, but memory use more efficient. This was at a time when memory size was considerably smaller, and at a premium, than that which users are used to today.<ref name="Osborne"/>{{rp|5–26}} ====Porting older software==== Small programs could ignore the segmentation and just use plain 16-bit addressing. This allows [[8-bit]] software to be quite easily ported to the 8086. The authors of MS-DOS took advantage of this by providing an [[Application Programming Interface]] very similar to [[CP/M]] as well as including the simple ''.com'' executable file format, identical to CP/M. This was important when the 8086 and MS-DOS were new, because it allowed many existing CP/M (and other) applications to be quickly made available, greatly easing acceptance of the new platform. ===Example code=== The following 8086/8088 [[assembly language|assembler]] source code is for a subroutine named <code>_memcpy</code> that copies a block of data bytes of a given size from one location to another. The data block is copied one byte at a time, and the data movement and looping logic utilizes 16-bit operations. <!--NOTE: This is not intended to be optimized code, but to illustrate the variety of instructions available on the CPU--> <!--NOTE: The hex codes were assembled by hand, so there may be errors--> {| | <!--NOTE: DO NOT REMOVE BLANK LINES--><pre> 0000:1000 0000:1000 0000:1000 55 0000:1001 89 E5 0000:1003 06 0000:1004 8B 4E 06 0000:1007 E3 11 0000:1009 8B 76 04 0000:100C 8B 7E 02 0000:100F 1E 0000:1010 07 0000:1011 8A 04 0000:1013 88 05 0000:1015 46 0000:1016 47 0000:1017 49 0000:1018 75 F7 0000:101A 07 0000:101B 5D 0000:101C 29 C0 0000:101E C3 0000:101F </pre> | <source lang="nasm"> ; _memcpy(dst, src, len) ; Copy a block of memory from one location to another. ; ; Entry stack parameters ; [BP+6] = len, Number of bytes to copy ; [BP+4] = src, Address of source data block ; [BP+2] = dst, Address of target data block ; ; Return registers ; AX = Zero org 1000h ; Start at 0000:1000h _memcpy proc push bp ; Set up the call frame mov bp,sp push es ; Save ES mov cx,[bp+6] ; Set CX = len jcxz done ; If len = 0, return mov si,[bp+4] ; Set SI = src mov di,[bp+2] ; Set DI = dst push ds ; Set ES = DS pop es loop mov al,[si] ; Load AL from [src] mov [di],al ; Store AL to [dst] inc si ; Increment src inc di ; Increment dst dec cx ; Decrement len jnz loop ; Repeat the loop done pop es ; Restore ES pop bp ; Restore previous call frame sub ax,ax ; Set AX = 0 ret ; Return end proc </source> |} The code above uses the BP (base pointer) register to establish a [[call frame]], an area on the stack that contains all of the parameters and local variables for the execution of the subroutine. This kind of [[calling convention]] supports [[reentrancy (computing)|reentrant]] and [[recursion (computer science)|recursive]] code, and has been used by most ALGOL-like languages since the late 1950s. The above routine is a rather cumbersome way to copy blocks of data. The 8086 provides dedicated instructions for copying strings of bytes. These instructions assume that the source data is stored at DS:SI, the destination data is stored at ES:DI, and that the number of elements to copy is stored in CX. The above routine requires the source and the destination block to be in the same segment, therefore DS is copied to ES. The loop section of the above can be replaced by: {| | <pre> 0000:1011 FC 0000:1012 F2 0000:1013 A4 </pre> | <source lang=nasm> cld ; Copy towards higher addresses loop repnz ; Repeat until CX = 0 movsb ; Move the data block </source> |} This copies the block of data one byte at a time. The <code>REPNZ</code> instruction causes the following <code>MOVSB</code> to repeat until CX is zero, automatically incrementing SI and DI and decrementing CX as it repeats. Alternatively the <code>MOVSW</code> instruction can be used to copy 16-bit words (double bytes) at a time (in which case CX counts the number of words copied instead of the number of bytes). Most assemblers will properly recognize the <code>REPNZ</code> instruction if used as an in-line prefix to the <code>MOVSB</code> instruction, as in <code>REPNZ MOVSB</code>. This routine will operate correctly if interrupted, because the program counter will continue to point to the <code>REP</code> instruction until the block copy is completed. The copy will therefore continue from where it left off when the interrupt service routine returns control. ===Performance=== [[File:Intel 8086 block scheme.svg|thumb|405px|''Simplified block diagram over Intel 8088 (a variant of 8086); 1=main registers; 2=segment registers and IP; 3=address adder; 4=internal address bus; 5=instruction queue; 6=control unit (very simplified!); 7=bus interface; 8=internal databus; 9=ALU; 10/11/12=external address/data/control bus.'']] Although partly shadowed by other design choices in this particular chip, the [[multiplexed]] address and [[Bus (computing)|data buses]] limit performance slightly; transfers of 16-bit or 8-bit quantities are done in a four-clock memory access cycle, which is faster on 16-bit, although slower on 8-bit quantities, compared to many contemporary 8-bit based CPUs. As instructions vary from one to six bytes, fetch and execution are made [[Concurrency (computer science)|concurrent]] and decoupled into separate units (as it remains in today's x86 processors): The ''bus interface unit'' feeds the instruction stream to the ''execution unit'' through a 6-byte prefetch queue (a form of loosely coupled [[pipelining]]), speeding up operations on [[Processor register|register]]s and [[Operand|immediate]]s, while memory operations became slower (four years later, this performance problem was fixed with the [[80186]] and [[80286]]). However, the full (instead of partial) 16-bit architecture with a full width [[Arithmetic logic unit|ALU]] meant that 16-bit arithmetic instructions could now be performed with a single ALU cycle (instead of two, via internal carry, as in the 8080 and 8085), speeding up such instructions considerably. Combined with [[orthogonalization]]s of operations versus [[operand]] types and [[addressing mode]]s, as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below). {| class="wikitable" style="text-align: center; width: 100px; height: 50px;" |+ Execution times for typical instructions (in clock cycles)<ref>{{cite book|title=Microsoft Macro Assembler 5.0 Reference Manual|year=1987|publisher=Microsoft Corporation| quote=Timings and encodings in this manual are used with permission of Intel and come from the following publications: Intel Corporation. iAPX 86, 88, 186 and 188 User's Manual, Programmer's Reference, Santa Clara, Calif. 1986.|title-link=MASM}} (Similarly for iAPX 286, 80386, 80387.)</ref> |- style="vertical-align:bottom; border-bottom:3px double #999;" !align=left | instruction !align=left | register-register !align=left | register immediate !align=left | register-memory !align=left | memory-register !align=left | memory-immediate |- style="vertical-align:top; border-bottom:1px solid #999;" |mov || 2 || 4|| 8+EA || 9+EA || 10+EA |- style="vertical-align:top; border-bottom:1px solid #999;" |ALU || 3 ||4|| 9+EA, || 16+EA,|| 17+EA |- style="vertical-align:top; border-bottom:1px solid #999;" |jump || colspan="5" | ''register'' => 11 ; ''label'' => 15 ; ''condition,label'' => 16 |- style="vertical-align:top; border-bottom:1px solid #999;" |integer multiply || colspan="5" | 70~160 (depending on operand ''data'' as well as size) ''including'' any EA |- style="vertical-align:top; border-bottom:1px solid #999;" |integer divide || colspan="5" | 80~190 (depending on operand ''data'' as well as size) ''including'' any EA |} * EA = time to compute effective address, ranging from 5 to 12 cycles. * Timings are best case, depending on prefetch status, instruction alignment, and other factors. As can be seen from these tables, operations on registers and immediates were fast (between 2 and 4 cycles), while memory-operand instructions and jumps were quite slow; jumps took more cycles than on the simple [[Intel 8080|8080]] and [[Intel 8085|8085]], and the 8088 (used in the IBM PC) was additionally hampered by its narrower bus. The reasons why most memory related instructions were slow were threefold: * Loosely coupled fetch and execution units are efficient for instruction prefetch, but not for jumps and random data access (without special measures). * No dedicated address calculation adder was afforded; the microcode routines had to use the main ALU for this (although there was a dedicated ''segment'' + ''offset'' adder). * The address and data buses were [[multiplexing|multiplex]]ed, forcing a slightly longer (33~50%) bus cycle than in typical contemporary 8-bit processors. However, memory access performance was drastically enhanced with Intel's next generation of 8086 family CPUs. The [[Intel 80186|80186]] and [[Intel 80286|80286]] both had dedicated address calculation hardware, saving many cycles, and the 80286 also had separate (non-multiplexed) address and data buses. ===Floating point=== The 8086/8088 could be connected to a mathematical coprocessor to add hardware/microcode-based [[floating-point]] performance. The [[Intel 8087]] was the standard math coprocessor for the 8086 and 8088, operating on 80-bit numbers. Manufacturers like [[Cyrix]] (8087-compatible) and [[Weitek]] (''not'' 8087-compatible) eventually came up with high-performance floating-point coprocessors that competed with the 8087, as well as with the subsequent, higher-performing [[Intel 80387]]. ==Chip versions== The clock frequency was originally limited to 5&nbsp;MHz,<ref group="note" >(IBM PC used 4.77&nbsp;MHz, 4/3 the standard NTSC [[color burst]] frequency)</ref> but the last versions in [[HMOS]] were specified for 10&nbsp;MHz. HMOS-III and [[CMOS]] versions were manufactured for a long time (at least a while into the 1990s) for [[embedded system]]s, although its successor, the [[Intel 80186|80186]]/[[Intel 80188|80188]] (which includes some on-chip peripherals), has been more popular for embedded use. The 80C86, the CMOS version of the 8086, was used in the [[GRiDPad]], [[Toshiba T1200]], [[HP 110]], and finally the 1998–1999 [[Lunar Prospector]]. For the packaging, the Intel 8086 was available both in ceramic and plastic DIP packages. {| align="center" | [[Image:Intel_D8086_CS.jpg|thumb|A ceramic D8086 variant]] | [[Image:Intel_P8086.jpg|thumb|A plastic P8086 variant]] |} ===List of Intel 8086=== {| class="wikitable" |- ! Model number ! Frequency ! Technology ! Temperature range ! Date of release ! Price (USD){{ref|quantity}} |- | 8086 | 5&nbsp;MHz | HMOS | 0&nbsp;°C to 70&nbsp;°C<ref name="Intel Preview Special Issue 1980, page 29">8086 Available for industrial environment, Intel Preview Special Issue: 16-Bit Solutions, Intel Corporation, May/June 1980, page 29.</ref> | June 8, 1978<ref>[http://www.intel.com/pressroom/kits/quickrefyr.htm#1978 View Processors Chronologically by Date of Introduction:]</ref> | 86.65<ref>The 8086 Family: Concepts and realities, Intel Preview Special Issue: 16-Bit Solutions, Intel Corporation, May/June 1980, page 19.</ref> |- | 8086-1 | 10&nbsp;MHz | HMOS II | Commercial | | |- | 8086-2 | 8&nbsp;MHz | HMOS II | Commercial | May/June 1980<ref name="Intel Preview Special Issue 1980, page 17">New 8086 family products boost processor performance by 50 percent, Intel Preview Special Issue: 16-Bit Solutions, Intel Corporation, May/June 1980, page 17.</ref> | 200<ref name="Intel Preview Special Issue 1980, page 17"/> |- | 8086-4 | 4&nbsp;MHz | HMOS | Commercial | | |- | I8086 | | | −40&nbsp;°C to +85&nbsp;°C<ref name="Intel Preview Special Issue 1980, page 29"/> | May/June 1980<ref name="Intel Preview Special Issue 1980, page 29"/> | 173.25<ref name="Intel Preview Special Issue 1980, page 29"/> |} # {{note|quantity}} In quantity of 100. ===Derivatives and clones=== [[File:KL USSR KP1810BM86.jpg|thumb|Soviet clone [[K1810VM86]]]] [[File:Oki 80c86a.jpg|thumb|[[Oki Electric Industry|OKI]] M80C86A [[QFP|QFP-56]]]] [[File:UPD8086D-2 NEC 1984year 19week JAPAN.JPG|thumb|NEC μPD8086D-2 (8&nbsp;MHz) from the year 1984, week 19 JAPAN (clone of Intel D8086-2)]] Compatible—and, in many cases, enhanced—versions were manufactured by [[Fujitsu]], [[Harris Corporation|Harris]]/[[Intersil]], [[Oki Electric Industry|OKI]], [[Siemens AG]], [[Texas Instruments]], [[NEC]], [[Mitsubishi]], and [[AMD]]. For example, the [[NEC V20]] and [[NEC V30]] pair were hardware-compatible with the 8088 and 8086 even though NEC made original Intel clones μPD8088D and μPD8086D respectively, but incorporated the instruction set of the 80186 along with some (but not all) of the 80186 speed enhancements, providing a drop-in capability to upgrade both instruction set and processing speed without manufacturers having to modify their designs. Such relatively simple and low-power 8086-compatible processors in CMOS are still used in embedded systems. The electronics industry of the [[Soviet Union]] was able to replicate the 8086 through {{citation needed-span|both [[industrial espionage]] and reverse engineering|date=October 2013}}. The resulting chip, [[K1810VM86]], was binary and pin-compatible with the 8086. i8086 and i8088 were respectively the cores of the Soviet-made PC-compatible [[EC1831]] and [[EC1832]] desktops. (EC1831 is the EC identification of IZOT 1036C and EC1832 is the EC identification of IZOT 1037C, developed and manufactured in Bulgaria. EC stands for Единая Система.) However, the EC1831 computer (IZOT 1036C) had significant hardware differences from the IBM PC prototype. The EC1831 was the first PC-compatible computer with dynamic bus sizing (US Pat. No 4,831,514). Later some of the EC1831 principles were adopted in PS/2 (US Pat. No 5,548,786) and some other machines (UK Patent Application, Publication No. GB-A-2211325, Published June 28, 1989). ==Support chips== * [[Intel 8237]]: direct memory access (DMA) controller * [[Intel 8251]]: universal synchronous/asynchronous receiver/transmitter at 19.2 kbit/s * [[Intel 8253]]: programmable interval timer, 3x 16-bit max 10&nbsp;MHz * [[Intel 8255]]: programmable peripheral interface, 3x 8-bit I/O pins used for printer connection etc. * [[Intel 8259]]: programmable interrupt controller * [[Intel 8279]]: keyboard/display controller, scans a keyboard matrix and display matrix like [[Seven-segment display|7-seg]] * [[Intel 8282]]/[[Intel 8283|8283]]: 8-bit latch * [[Intel 8284]]: clock generator * [[Intel 8286]]/[[Intel 8287|8287]]: bidirectional 8-bit driver. In 1980 both Intel I8286/I8287 (industrial grade) version were available for 16.25 USD in quantities of 100.<ref name="Intel Preview Special Issue 1980, page 29"/> * [[Intel 8288]]: bus controller * [[Intel 8289]]: bus arbiter * [[Floppy-disk controller|NEC µPD765 or Intel 8272A]]: floppy controller<!--also NE72065--><ref>{{cite web|title=The floppy controller evolution &#124; OS/2 Museum |date=2011-05-26 |accessdate=2016-05-12 |url=http://www.os2museum.com/wp/the-floppy-controller-evolution/ |quote=In the original IBM PC (1981) and PC/XT (1983), the FDC was physically located on a separate diskette adapter card. The FDC itself was a NEC µPD765A or a compatible part, such as the Intel 8272A.}}</ref> ==Microcomputers using the 8086== * The Intel [[Multibus]]-compatible [[single-board computer]] ISBC 86/12 was announced in 1978.<ref>{{cite journal | title = Intel Adds 16-Bit Single Board | journal = Computerworld | date = December 11, 1978 | pages = 86 | volume = XII | issue = 50 | issn = 0010-4841 | url = https://books.google.com/books?id=07X0ovA_MmEC&pg=PA86#v=onepage&q&f=false | last1 = Enterprise | first1 = I.D.G }}</ref> * The [[Xerox NoteTaker]] was one of the earliest [[portable computer]] designs in 1978 and used three 8086 chips (as CPU, graphics processor, and I/O processor), but never entered commercial production. * [[Seattle Computer Products]] shipped [[S-100 bus]] based 8086 systems (SCP200B) as early as November 1979. * The Norwegian [[Mycron]] 2000, introduced in 1980. * One of the most influential microcomputers of all, the [[IBM PC]], used the [[Intel 8088]], a version of the 8086 with an 8-bit [[Bus (computing)|data bus]] (as mentioned above). * The first [[Compaq Deskpro]] used an 8086 running at 7.16&nbsp;MHz, but was compatible with add-in cards designed for the 4.77&nbsp;MHz [[IBM PC XT]] and could switch the CPU down to the lower speed (which also switched in a memory bus buffer to simulate the 8088's slower access) to avoid software timing issues. * An 8&nbsp;MHz 8086-2 was used in the [[Olivetti M24|AT&T 6300 PC]] (built by [[Olivetti]], and known globally under several brands and model numbers), an IBM PC-compatible desktop microcomputer. The M24 / PC 6300 has IBM PC/XT compatible 8-bit expansion slots, but some of them have a proprietary extension providing the full 16-bit data bus of the 8086 CPU (similar in concept to the 16-bit slots of the [[IBM PC AT]], but different in the design details, and physically incompatible), and all system peripherals including the onboard video system also enjoy 16-bit data transfers. The later Olivetti M24SP featured an 8086-2 running at the full maximum 10&nbsp;MHz. * The [[IBM Personal System/2|IBM PS/2]] models 25 and 30 were built with an 8&nbsp;MHz 8086. * The Amstrad/Schneider [[Amstrad PC1512|PC1512]], [[Amstrad PC1640|PC1640]], [[Amstrad PC2086|PC2086]], [[Amstrad PC3086|PC3086]] and [[Amstrad PC5086|PC5086]] all used 8086 CPUs at 8&nbsp;MHz. * The [[NEC PC-9801]]. * The [[Tandy 1000]] SL-series and RL machines used 9.47&nbsp;MHz 8086 CPUs. * The [[IBM Displaywriter]] word processing machine<ref name = "InfoWorld Aug 1982" >{{cite journal | last = Zachmann | first = Mark | title = Flaws in IBM Personal Computer frustrate critic | journal = InfoWorld | volume = 4 | issue = 33 | pages =57–58 | date = August 23, 1982 | url = https://books.google.com/books?id=VDAEAAAAMBAJ&pg=PA57| issn = 0199-6649 | quote = the IBM Displaywriter is noticeably more expensive than other industrial micros that use the 8086. }}</ref> and the Wang Professional Computer, manufactured by [[Wang Laboratories]], also used the 8086. * [[NASA]] used original 8086 CPUs on equipment for ground-based maintenance of the [[Space Shuttle Discovery]] until the end of the space shuttle program in 2011. This decision was made to prevent [[software regression]] that might result from upgrading or from switching to imperfect clones.<ref>[https://www.nytimes.com/2002/05/12/technology/ebusiness/12NASA.html?pagewanted=2 For Old Parts, NASA Boldly Goes ... on eBay], May 12, 2002.</ref> * KAMAN Process and Area Radiation Monitors<ref>Kaman Tech. Manual</ref> ==See also== * [[Transistor count]] * [[iAPX]], for the iAPX name ==Notes== {{Reflist|group=note|2}} ==References== {{Reflist|35em}} ==External links== {{Commons category}} * [http://datasheets.chipdb.org/Intel/x86/808x/datashts/8086 Intel datasheets] * [http://www.cpu-world.com/CPUs/8086/ List of 8086 CPUs and their clones at CPUworld.com] * [http://www.cpu-world.com/info/Pinouts/8086.html 8086 Pinouts] * [http://www.8085projects.info/post/Maximum-Mode-Interface.aspx Maximum Mode Interface] * [http://matthieu.benoit.free.fr/cross/data_sheets/Intel_8086_users_manual.htm The 8086 User's manual October 1979 INTEL Corporation] ([[PDF]] document) * [http://www.shubhsblog.com/category/8086-programs/ 8086 program codes using emu8086 (Version 4.08) Emulator] * [http://sourceforge.net/p/fake86/code/ci/master/tree/src/fake86/cpu.c Intel 8086/80186 emulator written in C, this file is part of a larger PC emulator] {{Intel processors|discontinued}} {{Authority control}} [[Category:Computer-related introductions in 1978]] [[Category:Intel x86 microprocessors|80086]]<!--Note: NOT a typo for 8086, this is done for numberical ordering of categories-->'
Unified diff of changes made by edit (edit_diff)
'@@ -182,17 +182,8 @@ The has eight more or less general 16-bit [[processor register|registers]] (including the [[Stack-based memory allocation|stack pointer]] but excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as twice as many 8-bit registers (see figure) while the other four, SI, DI, BP, SP, are 16-bit only. -Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the ''destination'', while the other operand, the ''source'', can be either ''register'' or ''immediate''. A single memory location can also often be used as both ''source'' and ''destination'' which, among other factors, further contributes to a [[code density]] comparable to (and often better than) most eight-bit machines at the time. - -The degree of generality of most registers are much greater than in the 8080 or 8085. However, 8086 registers were more specialized than in most contemporary [[minicomputer]]s and are also used implicitly by some instructions. While perfectly sensible for the assembly programmer, this makes register allocation for compilers more complicated compared to more orthogonal 16-bit and 32-bit processors of the time such as the [[PDP-11]], [[VAX]], [[68000]], [[32016]] etc. On the other hand, being more regular than the rather minimalistic but ubiquitous 8-bit microprocessors such as the [[MOS Technology 6502|6502]], [[Motorola 6800|6800]], [[6809]], [[Intel 8085|8085]], [[MCS-48]], [[Intel 8051|8051]], and other contemporary accumulator based machines, it is significantly easier to construct an efficient [[code generator]] for the 8086 architecture. - -Another factor for this is that the 8086 also introduced some new instructions (not present in the 8080 and 8085) to better support stack-based high-level programming languages such as Pascal and [[PL/M]]; some of the more useful instructions are '''push''' ''mem-op'', and '''ret''' ''size'', supporting the "Pascal [[calling convention]]" directly. (Several others, such as '''push'''&nbsp;''immed'' and '''enter''', were added in the subsequent 80186, 80286, and 80386 processors.) - -A 64&nbsp;KB (one segment) [[Stack (data structure)|stack]] growing towards lower addresses is supported in [[computer hardware|hardware]]; 16-bit words are pushed onto the stack, and the top of the stack is pointed to by SS:SP. There are 256&nbsp;[[interrupt]]s, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the [[return address]]es. - -The 8086 has 64&nbsp;K of 8-bit (or alternatively 32&nbsp;K of 16-bit word) [[I/O port]] space. +Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the ''destination'', while the other operand, the ''source'', can be either ''register'' or ''immediate''. A single memory location can also often be used as both ''source'' and ''destination'' which, among other factors, further contributes to a [[code density]] comparable to (and often better than) most ===Flags=== -8086 has a 16-bit [[status register|flags register]]. Nine of these condition code flags are active, and indicate the current state of the processor: [[Carry flag]] (CF), [[Parity flag]] (PF), [[Auxiliary flag|Auxiliary carry flag]] (AF), [[Zero flag]] (ZF), [[Sign flag]] (SF), [[Trap flag]] (TF), [[IF (x86 flag)|Interrupt flag]] (IF), [[Direction flag]] (DF), and [[Overflow flag]] (OF). -Also referred to as the status word, the layout of the flags register is as follows:<ref>{{Cite book|url=https://www.worldcat.org/oclc/11091251|title=IAPX 86, 88, 186, and 188 user's manual : programmer's reference|others=Intel Corporation.|isbn=978-0835930352|location=Santa Clara, CA|oclc=11091251}}</ref>{{Rp|3-5}} +NUN {| class="wikitable" ! Bit '
New page size (new_size)
46311
Old page size (old_size)
48882
Size change in edit (edit_delta)
-2571
Lines added in edit (added_lines)
[ 0 => 'Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the ''destination'', while the other operand, the ''source'', can be either ''register'' or ''immediate''. A single memory location can also often be used as both ''source'' and ''destination'' which, among other factors, further contributes to a [[code density]] comparable to (and often better than) most ', 1 => 'NUN' ]
Lines removed in edit (removed_lines)
[ 0 => 'Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the ''destination'', while the other operand, the ''source'', can be either ''register'' or ''immediate''. A single memory location can also often be used as both ''source'' and ''destination'' which, among other factors, further contributes to a [[code density]] comparable to (and often better than) most eight-bit machines at the time.', 1 => false, 2 => 'The degree of generality of most registers are much greater than in the 8080 or 8085. However, 8086 registers were more specialized than in most contemporary [[minicomputer]]s and are also used implicitly by some instructions. While perfectly sensible for the assembly programmer, this makes register allocation for compilers more complicated compared to more orthogonal 16-bit and 32-bit processors of the time such as the [[PDP-11]], [[VAX]], [[68000]], [[32016]] etc. On the other hand, being more regular than the rather minimalistic but ubiquitous 8-bit microprocessors such as the [[MOS Technology 6502|6502]], [[Motorola 6800|6800]], [[6809]], [[Intel 8085|8085]], [[MCS-48]], [[Intel 8051|8051]], and other contemporary accumulator based machines, it is significantly easier to construct an efficient [[code generator]] for the 8086 architecture.', 3 => false, 4 => 'Another factor for this is that the 8086 also introduced some new instructions (not present in the 8080 and 8085) to better support stack-based high-level programming languages such as Pascal and [[PL/M]]; some of the more useful instructions are '''push''' ''mem-op'', and '''ret''' ''size'', supporting the "Pascal [[calling convention]]" directly. (Several others, such as '''push'''&nbsp;''immed'' and '''enter''', were added in the subsequent 80186, 80286, and 80386 processors.)', 5 => false, 6 => 'A 64&nbsp;KB (one segment) [[Stack (data structure)|stack]] growing towards lower addresses is supported in [[computer hardware|hardware]]; 16-bit words are pushed onto the stack, and the top of the stack is pointed to by SS:SP. There are 256&nbsp;[[interrupt]]s, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the [[return address]]es.', 7 => false, 8 => 'The 8086 has 64&nbsp;K of 8-bit (or alternatively 32&nbsp;K of 16-bit word) [[I/O port]] space.', 9 => '8086 has a 16-bit [[status register|flags register]]. Nine of these condition code flags are active, and indicate the current state of the processor: [[Carry flag]] (CF), [[Parity flag]] (PF), [[Auxiliary flag|Auxiliary carry flag]] (AF), [[Zero flag]] (ZF), [[Sign flag]] (SF), [[Trap flag]] (TF), [[IF (x86 flag)|Interrupt flag]] (IF), [[Direction flag]] (DF), and [[Overflow flag]] (OF).', 10 => 'Also referred to as the status word, the layout of the flags register is as follows:<ref>{{Cite book|url=https://www.worldcat.org/oclc/11091251|title=IAPX 86, 88, 186, and 188 user's manual : programmer's reference|others=Intel Corporation.|isbn=978-0835930352|location=Santa Clara, CA|oclc=11091251}}</ref>{{Rp|3-5}}' ]
Whether or not the change was made through a Tor exit node (tor_exit_node)
false
Unix timestamp of change (timestamp)
1538467631