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In 1972, Intel launched the [[Intel 8008|8008]], the first 8-bit microprocessor.<ref>using enhancement load [[PMOS logic]] (demanding 14V, achieving TTL-compatibility by having V<sub>CC</sub> at +5V and V<sub>DD</sub> at -9V)</ref> It implemented an [[instruction set]] designed by [[Datapoint]] corporation with programmable [[Computer terminal|CRT terminals]] in mind, that also proved to be fairly general purpose. The device needed several additional [[Integrated Circuit|IC]]s to produce a functional computer, in part due to its small 18-pin "memory-package", which ruled out the use of a separate address bus (Intel was primarily a [[DRAM]] manufacturer at the time).
In 1972, Intel launched the [[Intel 8008|8008]], the first 8-bit microprocessor.<ref>using enhancement load [[PMOS logic]] (demanding 14V, achieving TTL-compatibility by having V<sub>CC</sub> at +5V and V<sub>DD</sub> at -9V)</ref> It implemented an [[instruction set]] designed by [[Datapoint]] corporation with programmable [[Computer terminal|CRT terminals]] in mind, that also proved to be fairly general purpose. The device needed several additional [[Integrated Circuit|IC]]s to produce a functional computer, in part due to its small 18-pin "memory-package", which ruled out the use of a separate address bus (Intel was primarily a [[DRAM]] manufacturer at the time).


Two years later, in 1974, Intel launched the [[Intel 8080|8080]],<ref>using non-saturated enhancement load [[NMOS logic]] (demanding a higher gate voltage for the load transistor-gates)</ref> employing the new 40-pin [[Dual in-line package|DIL package]]s originally developed for [[calculator]] ICs to enable a separate address bus. It had an extended instruction set that was [[Source compatible|source]]- (not [[binary compatible|binary]]-) compatible with the 8008 and also included some 16-bit instructions to make programming easier. The 8080 device, often described as the first truly useful microprocessor, was eventually replaced by the [[Depletion-load NMOS logic|depletion-load]] based [[Intel 8085|8085]] (1977) which could cope with a single 5V power supply instead of the three different operating voltages of earlier chips.<ref>made possible with depletion load nMOS logic (the 8085 was later made using HMOS processing, just like the 8086)</ref> Other well known 8-bit microprocessors that emerged during these years were [[Motorola 6800]] (1974), [[PIC microcontroller|General Instrument PIC16X]] (1975), [[MOS Technology 6502]] (1975), [[Zilog Z80]] (1976), and [[Motorola 6809]] (1978).
Two years later, in 1974, Intel launched the [[Intel 8080|8080]],<ref>using non-saturated enhancement load [[NMOS logic]] (demanding a higher gate voltage for the load transistor-gates)</ref> employing the new 40-pin [[Dual in-line package|DIL package]]s originally developed for [[calculator]] ICs to enable a separate address bus. It had an extended instruction set that was [[Source compatible|source]]- (not [[binary compatible|binary]]-) compatible with the 8008 and also included some 16-bit instructions to make programming easier. The 8080 device, often described as the first truly useful microprocessor, was eventually replaced by the [[Depletion-load NMOS logic|depletion-load]] based [[Intel 8085|8085]] (1977) which could cope with a single 5V power supply instead of the three different operating voltages of earlier chips.<ref>made possible with depletion load nMOS logic (the 8085 was later made using HMOS processing, just like the 8086)</ref> Other well known 8-bit microprocessors that emerged during these years were [[Motorola 6800]] (1974), [[PIC microcontroller|General Instrument PIC16X]] (1975), [[MOS Technology 6502]] (1975), [[Zilog Z80]] (1976), and [[Motorola 6809]] (1978).pppppppp


===The first x86 design===
===The first x86 design===

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'{{Infobox CPU |name = Intel 8086 |image = KL_Intel_D8086.jpg |caption = |produced-start = 1978 |produced-end = 1990s |slowest = 5 | slow-unit = MHz |fastest = 10 | fast-unit = MHz |manuf1 = [[Intel]], [[AMD]], [[NEC]], [[Fujitsu]], [[Harris Corporation|Harris]] ([[Intersil]]), [[Oki Electric Industry|OKI]], [[Siemens AG]], [[Texas Instruments]], [[Mitsubishi]]. |arch = [[x86-16]] |pack1 = 40 pin [[Dual in-line package|DIP]] |predecessor = ([[Intel 8080|8080]])<!-- not instruction set compatible --> |variant = [[Intel 8088|8088]] |successor = [[Intel 80186|80186]] | size-from = 3[[μm]] | transistors-from = 29,000 }} The '''8086'''<ref>{{cite web|title=Microprocessor Hall of Fame|url=http://www.intel.com/museum/online/hist%5Fmicro/hof/|publisher=Intel|accessdate=2007-08-11|archiveurl=http://web.archive.org/web/20070706032836/http://www.intel.com/museum/online/hist_micro/hof/|archivedate=2007-07-06}}</ref> (also called '''iAPX86''') is a [[16-bit]] [[microprocessor]] chip designed by [[Intel]] between early 1976 and mid-1978, when it was released. The 8086 gave rise to the [[x86 architecture]] of Intel's future processors. The [[Intel 8088]], released in 1979, was a slightly modified chip with an external 8-bit [[Bus (computing)|data bus]] (allowing the use of cheaper and fewer supporting logic chips<ref>It also permitted cheap 8080-family chips to be used (such as the 8254 CTC, [[Intel 8255|8255]] PIO, and 8259 PIC which were used in the IBM PC design). In addition, it made PCB layout simpler and boards cheaper, as well as demanding fewer (1- or 4-bit wide) DRAM chips.</ref>), and is notable as the processor used in the original [[IBM PC]]. ==History== ===Background=== In 1972, Intel launched the [[Intel 8008|8008]], the first 8-bit microprocessor.<ref>using enhancement load [[PMOS logic]] (demanding 14V, achieving TTL-compatibility by having V<sub>CC</sub> at +5V and V<sub>DD</sub> at -9V)</ref> It implemented an [[instruction set]] designed by [[Datapoint]] corporation with programmable [[Computer terminal|CRT terminals]] in mind, that also proved to be fairly general purpose. The device needed several additional [[Integrated Circuit|IC]]s to produce a functional computer, in part due to its small 18-pin "memory-package", which ruled out the use of a separate address bus (Intel was primarily a [[DRAM]] manufacturer at the time). Two years later, in 1974, Intel launched the [[Intel 8080|8080]],<ref>using non-saturated enhancement load [[NMOS logic]] (demanding a higher gate voltage for the load transistor-gates)</ref> employing the new 40-pin [[Dual in-line package|DIL package]]s originally developed for [[calculator]] ICs to enable a separate address bus. It had an extended instruction set that was [[Source compatible|source]]- (not [[binary compatible|binary]]-) compatible with the 8008 and also included some 16-bit instructions to make programming easier. The 8080 device, often described as the first truly useful microprocessor, was eventually replaced by the [[Depletion-load NMOS logic|depletion-load]] based [[Intel 8085|8085]] (1977) which could cope with a single 5V power supply instead of the three different operating voltages of earlier chips.<ref>made possible with depletion load nMOS logic (the 8085 was later made using HMOS processing, just like the 8086)</ref> Other well known 8-bit microprocessors that emerged during these years were [[Motorola 6800]] (1974), [[PIC microcontroller|General Instrument PIC16X]] (1975), [[MOS Technology 6502]] (1975), [[Zilog Z80]] (1976), and [[Motorola 6809]] (1978). ===The first x86 design=== The 8086 project started in May 1976 and was originally intended as a temporary substitute for the ambitious and delayed [[iAPX 432]] project. It was an attempt to draw attention from the less-delayed 16 and 32-bit processors of other manufacturers (such as [[Motorola]], [[Zilog]], and [[National Semiconductor]]) and at the same time to counter the threat from the [[Zilog Z80]] (designed by former Intel employees), which became very successful. Both the architecture and the physical chip were therefore developed rather quickly by a small group of people, and using the same basic [[microarchitecture]] elements and physical implementation techniques as employed for the slightly older [[Intel 8085|8085]] (and for which the 8086 also would function as a continuation). Marketed as [[Source code compatibility|source compatible]], the 8086 was designed so that [[assembly language]] for the 8008, 8080, or 8085 could be automatically converted into equivalent (sub-optimal) 8086 source code, with little or no hand-editing. The programming model and instruction set was (loosely) based on the 8080 in order to make this possible. However, the 8086 design was expanded to support full 16-bit processing, instead of the fairly basic 16-bit capabilities of the 8080/8085. New kinds of instructions were added as well; full support for signed integers, base+offset addressing, and self-repeating operations were akin to the [[Z80]] design<ref>[http://www.pcworld.com/article/146957/birth_of_a_standard_the_intel_8086_microprocessor.html Birth of a Standard: The Intel 8086 Microprocessor. Thirty years ago, Intel released the 8086 processor, introducing the x86 architecture that underlies every PC-Windows, Mac, or Linux-produced today], PC World, June 17, 2008</ref> but were all made slightly more general in the 8086. Instructions directly supporting [[nested function|nested]] [[ALGOL]]-family languages such as [[Pascal (programming language)|Pascal]] and [[PL/M]] were also added. According to principal architect [[Stephen P. Morse]], this was a result of a more software centric approach than in the design of earlier Intel processors (the designers had experience working with compiler implementations). Other enhancements included [[microcode]]d multiply and divide instructions and a bus-structure better adapted to future co-processors (such as [[Intel 8087|8087]] and [[Intel 8089|8089]]) and multiprocessor systems. The first revision of the instruction set and high level architecture was ready after about three months,<ref>Rev.0 of the instruction set and architecture was ready in about three months, according to Morse.</ref> and as almost no CAD-tools were used, four engineers and 12&nbsp;layout people were simultaneously working on the chip.<ref>Using [[rubylith]], light boards, rulers, electric erasers, and a [[digitizer]] (according to Jenny Hernandez, member of the 8086 design team, in a statement made on Intel's web-page for its 25th birthday).</ref> The 8086 took a little more than two years from idea to working product, which was considered rather fast for a complex design in 1976–1978. The 8086 was sequenced<ref>8086 used less microcode than many competitors designs, such as the MC68000 and others</ref> using a mixture of random logic<ref>Randall L. Geiger, Phillip E. Allen, Noel R. Strader ''VLSI design techniques for analog and digital circuits'', McGraw-Hill Book Co., 1990, ISBN 0070232539, page 779 "Random Logic vs. Structured Logic Forms", illustration of use of "random" describing CPU control logic </ref> and [[microcode]] and was implemented using depletion-load nMOS circuitry with approximately 20,000&nbsp;active [[transistor]]s (29,000 counting all [[Read only memory|ROM]] and [[Programmable logic array|PLA]] sites). It was soon moved to a new refined nMOS manufacturing process called [[HMOS]] (for High performance MOS) that Intel originally developed for manufacturing of fast [[static RAM]] products.<ref>Fast static RAMs in MOS technology (as fast as bipolar RAMs) was an important product for Intel during this period.</ref> This was followed by HMOS-II, HMOS-III versions, and, eventually, a fully static [[CMOS]] version for battery-powered devices, manufactured using Intel's [[CHMOS]] processes.<ref>CHMOS is intels name for CMOS circuits manufactured using processing steps very similar to [[HMOS]].</ref> The original chip measured 33&nbsp;mm² and minimum feature size was 3.2&nbsp;μm. The architecture was defined by Stephen P. Morse with some help and assistance by Bruce Ravenel (the architect of the 8087) in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development team<ref>Other members of the design team were Peter A.Stoll and Jenny Hernandez.</ref> and William Pohlman the manager for the project. The legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers; the 8086 also lent its last two digits to later extended versions of the design, such as the [[Intel 286]] and the [[Intel 386]], all of which eventually became known as the [[x86]] family. (Another reference is that the [[PCI Configuration Space|PCI Vendor ID]] for Intel devices is 8086<sub>h</sub>.) ==Details== [[Image:Wyprowadzenie mikroprocesora 8086.JPG|200px|thumb|The 8086 pin-assignments in min and max mode.]] {| class="infobox" style="font-size:88%;" |- | {| style="font-size:88%;" |- |colspan="17" | '''Main registers''' <br/> |- style="background:silver;color:black" | style="width:80px; text-align:center;" colspan="8"| AH | style="width:80px; text-align:center;" colspan="8"| AL | style="width:160px; background:white; color:black;"| '''AX''' (primary accumulator) |- style="background:silver;color:black" | style="width:80px; text-align:center;" colspan="8"| BH | style="width:80px; text-align:center;" colspan="8"| BL | style="width:160px; background:white; color:black;"| '''BX''' (base, accumulator) |- style="background:silver;color:black" | style="width:80px; text-align:center;" colspan="8"| CH | style="width:80px; text-align:center;" colspan="8"| CL | style="width:160px; background:white; color:black;"| '''CX''' (counter, accumulator) |- style="background:silver;color:black" | style="width:80px; text-align:center;" colspan="8"| DH | style="width:80px; text-align:center;" colspan="8"| DL | style="width:160px; background:white; color:black;"| '''DX''' (accumulator, other functions) |- |colspan="17" | '''Index registers''' <br/> |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| SI | style="width:160px; background:white; color:black;"| '''S'''ource '''I'''ndex |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| DI | style="width:160px; background:white; color:black;"| '''D'''estination '''I'''ndex |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| BP | style="width:160px; background:white; color:black;"| '''B'''ase '''P'''ointer |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| SP | style="width:160px; background:white; color:black;"| '''S'''tack '''P'''ointer |- |colspan="17" | '''Status register''' |- | style="width:10px; text-align:center;"| 15 | style="width:10px; text-align:center;"| 14 | style="width:10px; text-align:center;"| 13 | style="width:10px; text-align:center;"| 12 | style="width:10px; text-align:center;"| 11 | style="width:10px; text-align:center;"| 10 | style="width:10px; text-align:center;"| 9 | style="width:10px; text-align:center;"| 8 | style="width:10px; text-align:center;"| 7 | style="width:10px; text-align:center;"| 6 | style="width:10px; text-align:center;"| 5 | style="width:10px; text-align:center;"| 4 | style="width:10px; text-align:center;"| 3 | style="width:10px; text-align:center;"| 2 | style="width:10px; text-align:center;"| 1 | style="width:10px; text-align:center;"| 0 |style="width:160px; background:white; color:black" | (bit position) |- style="background:silver;color:black" | style="width:10px; text-align:center;"| - | style="width:10px; text-align:center;"| - | style="width:10px; text-align:center;"| - | style="width:10px; text-align:center;"| - | style="width:10px; text-align:center;"| [[Overflow flag|O]] | style="width:10px; text-align:center;"| [[Direction flag|D]] | style="width:10px; text-align:center;"| [[IF (x86 flag)|I]] | style="width:10px; text-align:center;"| [[Trap flag|T]] | style="width:10px; text-align:center;"| [[Sign flag|S]] | style="width:10px; text-align:center;"| [[Zero flag|Z]] | style="width:10px; text-align:center;"| - | style="width:10px; text-align:center;"| [[Adjust flag|A]] | style="width:10px; text-align:center;"| - | style="width:10px; text-align:center;"| [[Parity flag|P]] | style="width:10px; text-align:center;"| - | style="width:10px; text-align:center;"| [[Carry flag|C]] |style="width:160px; background:white; color:black" | Flags |- |colspan="17" | '''Segment register''' <br/> |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| CS | style="width:160px; background:white; color:black;"| '''C'''ode '''S'''egment |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| DS | style="width:160px; background:white; color:black;"| '''D'''ata '''S'''egment |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| ES | style="width:160px; background:white; color:black;"| '''E'''xtra'''S'''egment |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| SS | style="width:160px; background:white; color:black;"| '''S'''tack '''S'''egment |- |colspan="17" | '''Instruction pointer''' <br/> |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| IP | style="width:160px; background:white; color:black;"| '''I'''nstruction '''P'''ointer |} |- | |- |''The 8086 registers'' |} ===Buses and operation=== All internal registers, as well as internal and external data buses, were 16&nbsp;bits wide, firmly establishing the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus gave a 1&nbsp;[[Megabyte|MB]] physical address space (2<sup>20</sup> = 1,048,576). This address space was addressed by means of internal 'segmentation'. The data bus was [[multiplexed]] with the address bus in order to fit a standard 40-pin [[dual in-line package]]. 16-bit I/O addresses meant 64&nbsp;[[Kilobyte|KB]] of separate I/O space (2<sup>16</sup> = 65,536). The maximum '''linear''' address space was limited to 64&nbsp;KB, simply because internal registers were only 16&nbsp;bits wide. Programming over 64&nbsp;KB boundaries involved adjusting segment registers (see below) and remained so until the [[80386]] introduced more complex memory management hardware. Some of the control pins, which carry essential signals for all external operations, had more than one function depending upon whether the device was operated in ''min'' or ''max'' mode. The former was intended for small single processor systems whilst the latter was for medium or large systems, using more than one processor. ===Registers and instructions=== The 8086 had eight (more or less general) 16-bit [[processor register|registers]] including the [[Stack-based memory allocation|stack pointer]], but excluding the instruction pointer, flag register and segment registers. Four of them, AX, BX, CX, DX, could also be accessed as twice as many 8-bit registers (see figure) while the other four, BP, SI, DI, SP, were 16-bit only. Due to a compact encoding inspired by 8-bit processors, most instructions were one-address or two-address operations which means that the result were stored in one of the operands. At most one of the operands could be in memory, but this memory operand could also be the ''destination'', while the other operand, the ''source'', could be either ''register'' or ''immediate''. A single memory location could also often be used as both ''source'' and ''destination'' which, among other factors, further contributed to a [[code density]] comparable to (and often better than) most eight bit machines. Although the degree of generality of most registers were much greater than in the 8080 or 8085, it was still fairly low compared to the typical contemporary [[minicomputer]], and registers were also sometimes used implicitly by instructions. While perfectly sensible for the assembly programmer, this complicated register allocation for compilers compared to more regular 16- and 32-bit processors such as the [[PDP-11]], [[DEC VAX|VAX]], [[68000]], etc.; on the other hand, compared to semi-contemporary simple (but popular and ubiquitous) 8-bit microprocessors such as the [[MOS Technology 6502|6502]], [[Motorola 6809|6809]], or [[Intel 8085|8085]], it was significantly easier to generate code for the 8086 design. The 8086 also featured 64&nbsp;KB of 8-bit (or alternatively 32 K-word of 16-bit) [[I/O]] space. A 64&nbsp;KB (one segment) [[Stack (data structure)|stack]] growing towards lower addresses is supported by [[computer hardware]]; 2-byte words are pushed to the stack and the stack top (bottom) is pointed out by SS:SP. There are 256&nbsp;[[interrupt]]s, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the [[return address]]es. The processor had some new instructions (not present in the 8080 and 8085) to better support stack based high level programming languages such as Pascal and [[PL/M]]; some of the more useful ones were '''push''' ''mem-op'', and '''ret''' ''size'', supporting the "pascal [[calling convention]]" directly. (Several others, such as '''push''' ''immed'' and '''enter''', would be added in the subsequent 80186, 80286, and 80386 designs.) It also had a stack-marker mechanism. There are three control flags IF(Intrrupt Flag)TF(Trap Flag)DF(Direction flag). ===Flags=== 8086 has a 16-bit [[flag register]]. Out of these, 9 are active, and indicate the current state of the processor. These are — [[Carry flag]], [[Parity flag]], [[Auxiliary flag]], [[Zero flag]], [[Sign flag]], [[Trap flag]], [[IF (x86 flag) | Interrupt flag]], [[Direction flag]] and [[Overflow flag]]. ===Segmentation=== {{see also|x86 memory segmentation}} There are also four 16-bit [[x86 memory segmentation|segment]] registers (see figure) that allow the 8086 [[Central processing unit|CPU]] to access one [[megabyte]] of memory in an unusual way. Rather than concatenating the segment register with the address register, as in most processors whose address space exceeded their register size, the 8086 shifts the 16-bit segment only four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, each external address can be referred to by 2<sup>12</sup> = 4096 different segment:offset pairs. The 16-byte separation between segment bases (due to the 4-bit shift) is called a ''paragraph''. Although considered complicated and cumbersome by many programmers, this scheme also has advantages; a small program (less than 64&nbsp;KB) can be loaded starting at a fixed offset (such as 0) in its own segment, avoiding the need for [[Relocation (computer science)|relocation]], with at most 15&nbsp;bytes of alignment waste. Compilers for the 8086-family commonly support two types of [[pointer (computer programming)|pointer]], ''near'' and ''far''. Near pointers are 16-bit offsets implicitly associated with the program's code and/or data segment and so can be used only within parts of a program small enough to fit in one segment. Far pointers are 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also support ''huge'' pointers, which are like far pointers except that [[pointer arithmetic]] on a huge pointer treats it as a linear 20-bit pointer, while pointer arithmetic on a far pointer [[integer overflow|wraps around]] within its 16-bit offset without touching the segment part of the address. To avoid the need to specify ''near'' and ''far'' on numerous pointers, data structures, and functions, compilers also support "memory models" which specify default pointer sizes. The ''tiny'' (max 64K), ''small'' (max 128K), ''compact'' (data > 64K), ''medium'' (code > 64K), ''large'' (code,data > 64K), and ''huge'' (individual arrays > 64K) models cover practical combinations of near, far, and huge pointers for code and data. The ''tiny'' model means that code and data are shared in a single segment, just as in most 8-bit based processors, and can be used to build ''[[COM file|.com]]''-files for instance. Precompiled libraries often came in several versions compiled for different memory models. According to Morse et al., the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16&nbsp;MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1&nbsp;MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low-cost 40-pin package for the additional four address bus pins.<ref>Intel 8008 to 8086 by Stephen P. Morse et al.</ref> In principle, the address space of the x86 series ''could'' have been extended in later processors by increasing the shift value, as long as applications obtained their segments from the operating system and did not make assumptions about the equivalence of different segment:offset pairs.<ref>Some 80186 clones did change the shift value, but were never commonly used in desktop computers.</ref> In practice the use of "huge" pointers and similar mechanisms was widespread and the flat 32-bit addressing made possible with the 32-bit offset registers in the 80386 eventually extended the limited addressing range in a more general way (see below). ====Porting older software==== Small programs could ignore the segmentation and just use plain 16-bit addressing. This allowed [[8-bit]] software to be quite easily ported to the 8086. The authors of MS-DOS took advantage of this by providing an [[Application Programming Interface]] very similar to [[CP/M]] as well as including the simple ''.com'' executable file format, identical to CP/M. This was important when the 8086 and MS-DOS were new, because it allowed many existing CP/M (and other) applications to be quickly made available, greatly easing acceptance of the new platform. ===Performance=== Although partly shadowed by other design choices in this particular chip, the multiplexed bus limited performance slightly; transfers of 16-bit or 8-bit quantities were done in a four-clock memory access cycle (which was faster on 16-bit, although slower on 8-bit quantities, compared to typical contemporary "8-bit" CPUs). As instructions varied from one to six bytes, fetch and execution were made [[Concurrency (computer science)|concurrent]] (as it remains in today's x86 processors): The ''bus interface unit'' fed the instruction stream to the ''execution unit'' through a 6-byte prefetch queue (a form of loosely coupled [[pipelining]]), speeding up operations on [[Processor register|register]]s and [[Operand|immediate]]s, while memory operations unfortunately became slower; four years later, this performance problem was fixed with the [[80186]] and [[80286]]). However, the full (instead of partial) 16-bit architecture with a full width [[Arithmetic logic unit|ALU]] meant that 16-bit arithmetic instructions could now be performed with a single ALU cycle (instead of two, via carry), speeding up such instructions considerably. Combined with [[orthogonalization]]s of operations versus [[operand]]-types and [[addressing mode]]s, as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below). <center> {| class="wikitable" style="text-align: center; width: 100px; height: 50px;" |+ Execution times for typical instructions<br/>(in clock cycles)<ref>{{cite book|title=[[MASM|Microsoft Macro Assembler]] 5.0 Reference Manual|year=1987|publisher=Microsoft Corporation| quote=Timings and encodings in this manual are used with permission of Intel and come from the following publications: Intel Corporation. iAPX 86, 88, 186 and 188 User's Manual, Programmer's Reference, Santa Clara, Calif. 1986.}} (Similarly for iAPX 286, 80386, 80387.) </ref>{{page number|date=December 2010}} |- style="vertical-align:bottom; border-bottom:3px double #999;" !align=left | instruction !align=left | register-register !align=left | register immediate !align=left | register-memory !align=left | memory-register !align=left | memory-immediate |- style="vertical-align:top; border-bottom:1px solid #999;" |mov || 2 || 4|| 8+EA || 9+EA || 10+EA |- style="vertical-align:top; border-bottom:1px solid #999;" |ALU || 3 ||4|| 9+EA, || 16+EA,|| 17+EA |- style="vertical-align:top; border-bottom:1px solid #999;" |jump || colspan="5" | ''register'' => 11 ; ''label'' => 15 ; ''condition,label'' => 16 |- style="vertical-align:top; border-bottom:1px solid #999;" |integer multiply || colspan="5" | 70~160 (depending on operand ''data'' as well as size) plus EA |- style="vertical-align:top; border-bottom:1px solid #999;" |signed integer divide || colspan="5" | 80~190 (depending on operand ''data'' as well as size) plus EA |}</center> *EA = time to compute effective address, ranging from 5 to 12 cycles. *Timings are best case, depending on prefetch status, instruction alignment, and other factors. [[Image:Intel 8086 block scheme.svg|thumb|405px|''Simplified block diagram over Intel 8088 (a variant of 8086); 1=main registers; 2=segment registers and IP; 3=address adder; 4=internal address bus; 5=instruction queue; 6=control unit (very simplified!); 7=bus interface; 8=internal databus; 9=ALU; 10/11/12=external address/data/control bus.'']] As can be seen from these tables, operations on registers and immediates were fast (between 2 and 4 cycles), while memory-operand instructions and jumps were quite slow; jumps took more cycles than on the simple [[Intel 8080|8080]] and [[Intel 8085|8085]], and the 8088 (used in the IBM PC) was additionally hampered by its narrower bus. The reasons why most memory related instructions were slow were threefold: *Loosely-coupled fetch and execution units are efficient for instruction prefetch, but not for jumps and random data access (without special measures). *No dedicated address calculation adder was afforded; the microcode routines had to use the main ALU for this (although there was a dedicated ''segment'' + ''offset'' adder). *The address and data buses were [[multiplexing|multiplex]]ed, forcing a slightly longer (33~50%) bus cycle than in typical contemporary 8-bit processors. However, memory access performance was drastically enhanced with Intel's next generation chips. The [[Intel 80186|80186]] and [[Intel 80286|80286]] both had dedicated address calculation hardware, saving many cycles, and the 80286 also had separate (non-multiplexed) address and data buses. ===Floating point=== The 8086/8088 could be connected to a mathematical coprocessor to add hardware/microcode-based [[floating point]] performance. The [[Intel 8087]] was the standard math coprocessor for the 8086 and 8088, operating on 80-bit numbers. Manufacturers like [[Cyrix]] (8087-compatible) and [[Weitek]] (''non'' 8087-compatible) eventually came up with high performance floating point co-processors that competed with the 8087 as well as with the subsequent, higher performing [[Intel 80387]]. ==Chip versions== The clock frequency was originally limited to 5&nbsp;MHz (IBM PC used 4.77&nbsp;MHz, 4/3 the standard NTSC [[color burst]] frequency), but the last versions in [[HMOS]] were specified for 10&nbsp;MHz. HMOS-III and [[CMOS]] versions were manufactured for a long time (at least a while into the 1990s) for [[embedded system]]s, although its successor, the [[Intel 80186|80186]]/[[Intel 80188|80188]] (which includes some on-chip peripherals), has been more popular for embedded use. ===Derivatives and clones=== [[Image:KL USSR KP1810BM86.jpg|right|thumb|180px|Soviet clone KP1810BM86.]] [[Image:Oki 80c86a.jpg|thumb|right|180px|[[Oki Electric Industry|OKI]] M80C86A [[QFP|QFP-56]].]] Compatible—and, in many cases, enhanced—versions were manufactured by [[Fujitsu]], [[Harris Corporation|Harris]]/[[Intersil]], [[Oki Electric Industry|OKI]], [[Siemens AG]], [[Texas Instruments]], [[NEC]], [[Mitsubishi]], and [[AMD]]. For example, the [[NEC V20]] and NEC V30 pair were hardware compatible with the 8088 and 8086, respectively, but incorporated the instruction set of the 80186 along with some (but not all) of the 80186 speed enhancements, providing a drop-in capability to upgrade both instruction set and processing speed without manufacturers having to modify their designs. Such relatively simple and low-power 8086-compatible processors in CMOS are still used in embedded systems. The electronics industry of the [[Soviet Union]] was able to replicate the 8086 through both [[industrial espionage]] and reverse engineering. The resulting chip, [[K1810BM86]], was binary and pin-compatible with the 8086, but was not mechanically compatible because it used metric measurements. The 8088 and 8086 were the respective cores of the Soviet-made PC-compatible [[ES1840]] and [[ES1841]] desktops. However, these computers had significant hardware differences from their authentic prototypes, and the data/address bus circuitry was designed independently of Intel products.{{verify source|date=July 2011}} ES1841 was the first PC compatible computer with dynamic bus sizing (US Pat. No 4,831,514). Later some of the ES1841 principles were adopted in PS/2 (US Pat. No 5,548,786) and some other machines (UK Patent Application, Publication No. GB-A-2211325, Published June. 28, 1989). ==Microcomputers using the 8086== *The first commercial microcomputer built on the basis of the 8086 was the [[Mycron]] 2000. *One of the most influential microcomputers of all, the [[IBM PC]], used the [[Intel 8088]], a version of the 8086 with an eight-bit [[data bus]] (as mentioned above). *The first [[Compaq Deskpro]] used an 8086 running at 7.14&nbsp;MHz, (?) but was capable of running add-in cards designed for the 4.77&nbsp;MHz [[IBM PC XT]]. *An 8 MHz 8086 was used in the [[Olivetti M24|AT&T 6300 PC]] (built by [[Olivetti]]), an IBM PC-compatible office desktop microcomputer. The M24 / PC 6300 has IBM PC/XT compatible 8-bit expansion slots, but some of them have a proprietary extension providing the full 16-bit data bus of the 8086 CPU (similar in concept to the 16-bit slots of the [[IBM PC AT]], but different in the design details). *The [[IBM Personal System/2|IBM PS/2]] models 25 and 30 were built with an 8&nbsp;MHz 8086. *The Amstrad [[PC-1512|PC1512]], PC1640, PC2086, PC3086 and PC5086 all used 8086 CPUs at 8&nbsp;MHz. * The [[NEC PC-9801]]. *The [[Tandy 1000]] SL-series machines used 8086 CPUs. *The [[IBM Displaywriter]] word processing machine<ref name = "InfoWorld Aug 1982">{{cite journal | last = Zachmann | first = Mark| title = Flaws in IBM Personal Computer frustrate critic | journal = InfoWorld | volume = 4 | issue = 33 | pages = pp. 57-58 | publisher = Popular Computing | location = Palo Alto, CA | date = August 23, 1982| url = http://books.google.com/books?id=VDAEAAAAMBAJ&pg=PA57| issn = 0199-6649| quote = the IBM Displaywriter is noticeably more expensive than other industrial micros that use the 8086.}}</ref> and the Wang Professional Computer, manufactured by [[Wang Laboratories]], also used the 8086. *[[NASA]] used original 8086 CPUs on equipment for ground-based maintenance of the [[Space Shuttle Discovery]] until the end of the space shuttle program in 2011. This decision was made to prevent [[software regression]] that might result from upgrading or from switching to imperfect clones.<ref>[http://www.nytimes.com/2002/05/12/technology/ebusiness/12NASA.html?pagewanted=2 For Old Parts, NASA Boldly Goes ... on eBay], May 12, 2002</ref> ==See also== *[[x86 architecture]] ==Notes and references== {{Reflist|2}} ==External links== *[http://datasheets.chipdb.org/Intel/x86/808x/datashts/8086 Intel datasheets] *[http://www.cpu-world.com/CPUs/8086/ List of 8086 CPUs and their clones at CPUworld.com] *[http://www.cpu-world.com/info/Pinouts/8086.html 8086 Pinouts] {{Intel processors|discontinued}} [[Category:1978 introductions]] [[Category:Intel x86 microprocessors|8086]] [[ar:إنتل 8086]] [[bg:Intel 8086]] [[bs:Intel 8086]] [[ca:Intel 8086]] [[cs:Intel 8086]] [[de:Intel 8086]] [[et:Intel 8086]] [[el:Intel 8086]] [[es:Intel 8086 y 8088]] [[fr:Intel 8086]] [[ko:인텔 8086]] [[hr:Intel 8086]] [[id:Intel 8086]] [[it:Intel 8086]] [[he:8086 (מעבד)]] [[hu:Intel 8086]] [[ml:ഇന്റൽ 8086]] [[ms:Intel 8086]] [[nl:Intel 8086]] [[ja:Intel 8086]] [[no:Intel 8086]] [[pl:Intel 8086]] [[pt:Intel 8086]] [[ro:Intel 8086]] [[ru:Intel 8086]] [[sk:Intel 8086]] [[sr:Intel 8086]] [[fi:Intel 8086]] [[sv:Intel 8086]] [[tr:Intel 8086]] [[uk:Intel 8086]] [[zh:Intel 8086]]'
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'{{Infobox CPU |name = Intel 8086 |image = KL_Intel_D8086.jpg |caption = |produced-start = 1978 |produced-end = 1990s |slowest = 5 | slow-unit = MHz |fastest = 10 | fast-unit = MHz |manuf1 = [[Intel]], [[AMD]], [[NEC]], [[Fujitsu]], [[Harris Corporation|Harris]] ([[Intersil]]), [[Oki Electric Industry|OKI]], [[Siemens AG]], [[Texas Instruments]], [[Mitsubishi]]. |arch = [[x86-16]] |pack1 = 40 pin [[Dual in-line package|DIP]] |predecessor = ([[Intel 8080|8080]])<!-- not instruction set compatible --> |variant = [[Intel 8088|8088]] |successor = [[Intel 80186|80186]] | size-from = 3[[μm]] | transistors-from = 29,000 }} The '''8086'''<ref>{{cite web|title=Microprocessor Hall of Fame|url=http://www.intel.com/museum/online/hist%5Fmicro/hof/|publisher=Intel|accessdate=2007-08-11|archiveurl=http://web.archive.org/web/20070706032836/http://www.intel.com/museum/online/hist_micro/hof/|archivedate=2007-07-06}}</ref> (also called '''iAPX86''') is a [[16-bit]] [[microprocessor]] chip designed by [[Intel]] between early 1976 and mid-1978, when it was released. The 8086 gave rise to the [[x86 architecture]] of Intel's future processors. The [[Intel 8088]], released in 1979, was a slightly modified chip with an external 8-bit [[Bus (computing)|data bus]] (allowing the use of cheaper and fewer supporting logic chips<ref>It also permitted cheap 8080-family chips to be used (such as the 8254 CTC, [[Intel 8255|8255]] PIO, and 8259 PIC which were used in the IBM PC design). In addition, it made PCB layout simpler and boards cheaper, as well as demanding fewer (1- or 4-bit wide) DRAM chips.</ref>), and is notable as the processor used in the original [[IBM PC]]. ==History== ===Background=== In 1972, Intel launched the [[Intel 8008|8008]], the first 8-bit microprocessor.<ref>using enhancement load [[PMOS logic]] (demanding 14V, achieving TTL-compatibility by having V<sub>CC</sub> at +5V and V<sub>DD</sub> at -9V)</ref> It implemented an [[instruction set]] designed by [[Datapoint]] corporation with programmable [[Computer terminal|CRT terminals]] in mind, that also proved to be fairly general purpose. The device needed several additional [[Integrated Circuit|IC]]s to produce a functional computer, in part due to its small 18-pin "memory-package", which ruled out the use of a separate address bus (Intel was primarily a [[DRAM]] manufacturer at the time). Two years later, in 1974, Intel launched the [[Intel 8080|8080]],<ref>using non-saturated enhancement load [[NMOS logic]] (demanding a higher gate voltage for the load transistor-gates)</ref> employing the new 40-pin [[Dual in-line package|DIL package]]s originally developed for [[calculator]] ICs to enable a separate address bus. It had an extended instruction set that was [[Source compatible|source]]- (not [[binary compatible|binary]]-) compatible with the 8008 and also included some 16-bit instructions to make programming easier. The 8080 device, often described as the first truly useful microprocessor, was eventually replaced by the [[Depletion-load NMOS logic|depletion-load]] based [[Intel 8085|8085]] (1977) which could cope with a single 5V power supply instead of the three different operating voltages of earlier chips.<ref>made possible with depletion load nMOS logic (the 8085 was later made using HMOS processing, just like the 8086)</ref> Other well known 8-bit microprocessors that emerged during these years were [[Motorola 6800]] (1974), [[PIC microcontroller|General Instrument PIC16X]] (1975), [[MOS Technology 6502]] (1975), [[Zilog Z80]] (1976), and [[Motorola 6809]] (1978).pppppppp ===The first x86 design=== The 8086 project started in May 1976 and was originally intended as a temporary substitute for the ambitious and delayed [[iAPX 432]] project. It was an attempt to draw attention from the less-delayed 16 and 32-bit processors of other manufacturers (such as [[Motorola]], [[Zilog]], and [[National Semiconductor]]) and at the same time to counter the threat from the [[Zilog Z80]] (designed by former Intel employees), which became very successful. Both the architecture and the physical chip were therefore developed rather quickly by a small group of people, and using the same basic [[microarchitecture]] elements and physical implementation techniques as employed for the slightly older [[Intel 8085|8085]] (and for which the 8086 also would function as a continuation). Marketed as [[Source code compatibility|source compatible]], the 8086 was designed so that [[assembly language]] for the 8008, 8080, or 8085 could be automatically converted into equivalent (sub-optimal) 8086 source code, with little or no hand-editing. The programming model and instruction set was (loosely) based on the 8080 in order to make this possible. However, the 8086 design was expanded to support full 16-bit processing, instead of the fairly basic 16-bit capabilities of the 8080/8085. New kinds of instructions were added as well; full support for signed integers, base+offset addressing, and self-repeating operations were akin to the [[Z80]] design<ref>[http://www.pcworld.com/article/146957/birth_of_a_standard_the_intel_8086_microprocessor.html Birth of a Standard: The Intel 8086 Microprocessor. Thirty years ago, Intel released the 8086 processor, introducing the x86 architecture that underlies every PC-Windows, Mac, or Linux-produced today], PC World, June 17, 2008</ref> but were all made slightly more general in the 8086. Instructions directly supporting [[nested function|nested]] [[ALGOL]]-family languages such as [[Pascal (programming language)|Pascal]] and [[PL/M]] were also added. According to principal architect [[Stephen P. Morse]], this was a result of a more software centric approach than in the design of earlier Intel processors (the designers had experience working with compiler implementations). Other enhancements included [[microcode]]d multiply and divide instructions and a bus-structure better adapted to future co-processors (such as [[Intel 8087|8087]] and [[Intel 8089|8089]]) and multiprocessor systems. The first revision of the instruction set and high level architecture was ready after about three months,<ref>Rev.0 of the instruction set and architecture was ready in about three months, according to Morse.</ref> and as almost no CAD-tools were used, four engineers and 12&nbsp;layout people were simultaneously working on the chip.<ref>Using [[rubylith]], light boards, rulers, electric erasers, and a [[digitizer]] (according to Jenny Hernandez, member of the 8086 design team, in a statement made on Intel's web-page for its 25th birthday).</ref> The 8086 took a little more than two years from idea to working product, which was considered rather fast for a complex design in 1976–1978. The 8086 was sequenced<ref>8086 used less microcode than many competitors designs, such as the MC68000 and others</ref> using a mixture of random logic<ref>Randall L. Geiger, Phillip E. Allen, Noel R. Strader ''VLSI design techniques for analog and digital circuits'', McGraw-Hill Book Co., 1990, ISBN 0070232539, page 779 "Random Logic vs. Structured Logic Forms", illustration of use of "random" describing CPU control logic </ref> and [[microcode]] and was implemented using depletion-load nMOS circuitry with approximately 20,000&nbsp;active [[transistor]]s (29,000 counting all [[Read only memory|ROM]] and [[Programmable logic array|PLA]] sites). It was soon moved to a new refined nMOS manufacturing process called [[HMOS]] (for High performance MOS) that Intel originally developed for manufacturing of fast [[static RAM]] products.<ref>Fast static RAMs in MOS technology (as fast as bipolar RAMs) was an important product for Intel during this period.</ref> This was followed by HMOS-II, HMOS-III versions, and, eventually, a fully static [[CMOS]] version for battery-powered devices, manufactured using Intel's [[CHMOS]] processes.<ref>CHMOS is intels name for CMOS circuits manufactured using processing steps very similar to [[HMOS]].</ref> The original chip measured 33&nbsp;mm² and minimum feature size was 3.2&nbsp;μm. The architecture was defined by Stephen P. Morse with some help and assistance by Bruce Ravenel (the architect of the 8087) in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development team<ref>Other members of the design team were Peter A.Stoll and Jenny Hernandez.</ref> and William Pohlman the manager for the project. The legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers; the 8086 also lent its last two digits to later extended versions of the design, such as the [[Intel 286]] and the [[Intel 386]], all of which eventually became known as the [[x86]] family. (Another reference is that the [[PCI Configuration Space|PCI Vendor ID]] for Intel devices is 8086<sub>h</sub>.) ==Details== [[Image:Wyprowadzenie mikroprocesora 8086.JPG|200px|thumb|The 8086 pin-assignments in min and max mode.]] {| class="infobox" style="font-size:88%;" |- | {| style="font-size:88%;" |- |colspan="17" | '''Main registers''' <br/> |- style="background:silver;color:black" | style="width:80px; text-align:center;" colspan="8"| AH | style="width:80px; text-align:center;" colspan="8"| AL | style="width:160px; background:white; color:black;"| '''AX''' (primary accumulator) |- style="background:silver;color:black" | style="width:80px; text-align:center;" colspan="8"| BH | style="width:80px; text-align:center;" colspan="8"| BL | style="width:160px; background:white; color:black;"| '''BX''' (base, accumulator) |- style="background:silver;color:black" | style="width:80px; text-align:center;" colspan="8"| CH | style="width:80px; text-align:center;" colspan="8"| CL | style="width:160px; background:white; color:black;"| '''CX''' (counter, accumulator) |- style="background:silver;color:black" | style="width:80px; text-align:center;" colspan="8"| DH | style="width:80px; text-align:center;" colspan="8"| DL | style="width:160px; background:white; color:black;"| '''DX''' (accumulator, other functions) |- |colspan="17" | '''Index registers''' <br/> |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| SI | style="width:160px; background:white; color:black;"| '''S'''ource '''I'''ndex |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| DI | style="width:160px; background:white; color:black;"| '''D'''estination '''I'''ndex |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| BP | style="width:160px; background:white; color:black;"| '''B'''ase '''P'''ointer |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| SP | style="width:160px; background:white; color:black;"| '''S'''tack '''P'''ointer |- |colspan="17" | '''Status register''' |- | style="width:10px; text-align:center;"| 15 | style="width:10px; text-align:center;"| 14 | style="width:10px; text-align:center;"| 13 | style="width:10px; text-align:center;"| 12 | style="width:10px; text-align:center;"| 11 | style="width:10px; text-align:center;"| 10 | style="width:10px; text-align:center;"| 9 | style="width:10px; text-align:center;"| 8 | style="width:10px; text-align:center;"| 7 | style="width:10px; text-align:center;"| 6 | style="width:10px; text-align:center;"| 5 | style="width:10px; text-align:center;"| 4 | style="width:10px; text-align:center;"| 3 | style="width:10px; text-align:center;"| 2 | style="width:10px; text-align:center;"| 1 | style="width:10px; text-align:center;"| 0 |style="width:160px; background:white; color:black" | (bit position) |- style="background:silver;color:black" | style="width:10px; text-align:center;"| - | style="width:10px; text-align:center;"| - | style="width:10px; text-align:center;"| - | style="width:10px; text-align:center;"| - | style="width:10px; text-align:center;"| [[Overflow flag|O]] | style="width:10px; text-align:center;"| [[Direction flag|D]] | style="width:10px; text-align:center;"| [[IF (x86 flag)|I]] | style="width:10px; text-align:center;"| [[Trap flag|T]] | style="width:10px; text-align:center;"| [[Sign flag|S]] | style="width:10px; text-align:center;"| [[Zero flag|Z]] | style="width:10px; text-align:center;"| - | style="width:10px; text-align:center;"| [[Adjust flag|A]] | style="width:10px; text-align:center;"| - | style="width:10px; text-align:center;"| [[Parity flag|P]] | style="width:10px; text-align:center;"| - | style="width:10px; text-align:center;"| [[Carry flag|C]] |style="width:160px; background:white; color:black" | Flags |- |colspan="17" | '''Segment register''' <br/> |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| CS | style="width:160px; background:white; color:black;"| '''C'''ode '''S'''egment |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| DS | style="width:160px; background:white; color:black;"| '''D'''ata '''S'''egment |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| ES | style="width:160px; background:white; color:black;"| '''E'''xtra'''S'''egment |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| SS | style="width:160px; background:white; color:black;"| '''S'''tack '''S'''egment |- |colspan="17" | '''Instruction pointer''' <br/> |- style="background:silver;color:black" | style="width:160px; text-align:center;" colspan="16"| IP | style="width:160px; background:white; color:black;"| '''I'''nstruction '''P'''ointer |} |- | |- |''The 8086 registers'' |} ===Buses and operation=== All internal registers, as well as internal and external data buses, were 16&nbsp;bits wide, firmly establishing the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus gave a 1&nbsp;[[Megabyte|MB]] physical address space (2<sup>20</sup> = 1,048,576). This address space was addressed by means of internal 'segmentation'. The data bus was [[multiplexed]] with the address bus in order to fit a standard 40-pin [[dual in-line package]]. 16-bit I/O addresses meant 64&nbsp;[[Kilobyte|KB]] of separate I/O space (2<sup>16</sup> = 65,536). The maximum '''linear''' address space was limited to 64&nbsp;KB, simply because internal registers were only 16&nbsp;bits wide. Programming over 64&nbsp;KB boundaries involved adjusting segment registers (see below) and remained so until the [[80386]] introduced more complex memory management hardware. Some of the control pins, which carry essential signals for all external operations, had more than one function depending upon whether the device was operated in ''min'' or ''max'' mode. The former was intended for small single processor systems whilst the latter was for medium or large systems, using more than one processor. ===Registers and instructions=== The 8086 had eight (more or less general) 16-bit [[processor register|registers]] including the [[Stack-based memory allocation|stack pointer]], but excluding the instruction pointer, flag register and segment registers. Four of them, AX, BX, CX, DX, could also be accessed as twice as many 8-bit registers (see figure) while the other four, BP, SI, DI, SP, were 16-bit only. Due to a compact encoding inspired by 8-bit processors, most instructions were one-address or two-address operations which means that the result were stored in one of the operands. At most one of the operands could be in memory, but this memory operand could also be the ''destination'', while the other operand, the ''source'', could be either ''register'' or ''immediate''. A single memory location could also often be used as both ''source'' and ''destination'' which, among other factors, further contributed to a [[code density]] comparable to (and often better than) most eight bit machines. Although the degree of generality of most registers were much greater than in the 8080 or 8085, it was still fairly low compared to the typical contemporary [[minicomputer]], and registers were also sometimes used implicitly by instructions. While perfectly sensible for the assembly programmer, this complicated register allocation for compilers compared to more regular 16- and 32-bit processors such as the [[PDP-11]], [[DEC VAX|VAX]], [[68000]], etc.; on the other hand, compared to semi-contemporary simple (but popular and ubiquitous) 8-bit microprocessors such as the [[MOS Technology 6502|6502]], [[Motorola 6809|6809]], or [[Intel 8085|8085]], it was significantly easier to generate code for the 8086 design. The 8086 also featured 64&nbsp;KB of 8-bit (or alternatively 32 K-word of 16-bit) [[I/O]] space. A 64&nbsp;KB (one segment) [[Stack (data structure)|stack]] growing towards lower addresses is supported by [[computer hardware]]; 2-byte words are pushed to the stack and the stack top (bottom) is pointed out by SS:SP. There are 256&nbsp;[[interrupt]]s, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the [[return address]]es. The processor had some new instructions (not present in the 8080 and 8085) to better support stack based high level programming languages such as Pascal and [[PL/M]]; some of the more useful ones were '''push''' ''mem-op'', and '''ret''' ''size'', supporting the "pascal [[calling convention]]" directly. (Several others, such as '''push''' ''immed'' and '''enter''', would be added in the subsequent 80186, 80286, and 80386 designs.) It also had a stack-marker mechanism. There are three control flags IF(Intrrupt Flag)TF(Trap Flag)DF(Direction flag). ===Flags=== 8086 has a 16-bit [[flag register]]. Out of these, 9 are active, and indicate the current state of the processor. These are — [[Carry flag]], [[Parity flag]], [[Auxiliary flag]], [[Zero flag]], [[Sign flag]], [[Trap flag]], [[IF (x86 flag) | Interrupt flag]], [[Direction flag]] and [[Overflow flag]]. ===Segmentation=== {{see also|x86 memory segmentation}} There are also four 16-bit [[x86 memory segmentation|segment]] registers (see figure) that allow the 8086 [[Central processing unit|CPU]] to access one [[megabyte]] of memory in an unusual way. Rather than concatenating the segment register with the address register, as in most processors whose address space exceeded their register size, the 8086 shifts the 16-bit segment only four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, each external address can be referred to by 2<sup>12</sup> = 4096 different segment:offset pairs. The 16-byte separation between segment bases (due to the 4-bit shift) is called a ''paragraph''. Although considered complicated and cumbersome by many programmers, this scheme also has advantages; a small program (less than 64&nbsp;KB) can be loaded starting at a fixed offset (such as 0) in its own segment, avoiding the need for [[Relocation (computer science)|relocation]], with at most 15&nbsp;bytes of alignment waste. Compilers for the 8086-family commonly support two types of [[pointer (computer programming)|pointer]], ''near'' and ''far''. Near pointers are 16-bit offsets implicitly associated with the program's code and/or data segment and so can be used only within parts of a program small enough to fit in one segment. Far pointers are 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also support ''huge'' pointers, which are like far pointers except that [[pointer arithmetic]] on a huge pointer treats it as a linear 20-bit pointer, while pointer arithmetic on a far pointer [[integer overflow|wraps around]] within its 16-bit offset without touching the segment part of the address. To avoid the need to specify ''near'' and ''far'' on numerous pointers, data structures, and functions, compilers also support "memory models" which specify default pointer sizes. The ''tiny'' (max 64K), ''small'' (max 128K), ''compact'' (data > 64K), ''medium'' (code > 64K), ''large'' (code,data > 64K), and ''huge'' (individual arrays > 64K) models cover practical combinations of near, far, and huge pointers for code and data. The ''tiny'' model means that code and data are shared in a single segment, just as in most 8-bit based processors, and can be used to build ''[[COM file|.com]]''-files for instance. Precompiled libraries often came in several versions compiled for different memory models. According to Morse et al., the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16&nbsp;MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1&nbsp;MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low-cost 40-pin package for the additional four address bus pins.<ref>Intel 8008 to 8086 by Stephen P. Morse et al.</ref> In principle, the address space of the x86 series ''could'' have been extended in later processors by increasing the shift value, as long as applications obtained their segments from the operating system and did not make assumptions about the equivalence of different segment:offset pairs.<ref>Some 80186 clones did change the shift value, but were never commonly used in desktop computers.</ref> In practice the use of "huge" pointers and similar mechanisms was widespread and the flat 32-bit addressing made possible with the 32-bit offset registers in the 80386 eventually extended the limited addressing range in a more general way (see below). ====Porting older software==== Small programs could ignore the segmentation and just use plain 16-bit addressing. This allowed [[8-bit]] software to be quite easily ported to the 8086. The authors of MS-DOS took advantage of this by providing an [[Application Programming Interface]] very similar to [[CP/M]] as well as including the simple ''.com'' executable file format, identical to CP/M. This was important when the 8086 and MS-DOS were new, because it allowed many existing CP/M (and other) applications to be quickly made available, greatly easing acceptance of the new platform. ===Performance=== Although partly shadowed by other design choices in this particular chip, the multiplexed bus limited performance slightly; transfers of 16-bit or 8-bit quantities were done in a four-clock memory access cycle (which was faster on 16-bit, although slower on 8-bit quantities, compared to typical contemporary "8-bit" CPUs). As instructions varied from one to six bytes, fetch and execution were made [[Concurrency (computer science)|concurrent]] (as it remains in today's x86 processors): The ''bus interface unit'' fed the instruction stream to the ''execution unit'' through a 6-byte prefetch queue (a form of loosely coupled [[pipelining]]), speeding up operations on [[Processor register|register]]s and [[Operand|immediate]]s, while memory operations unfortunately became slower; four years later, this performance problem was fixed with the [[80186]] and [[80286]]). However, the full (instead of partial) 16-bit architecture with a full width [[Arithmetic logic unit|ALU]] meant that 16-bit arithmetic instructions could now be performed with a single ALU cycle (instead of two, via carry), speeding up such instructions considerably. Combined with [[orthogonalization]]s of operations versus [[operand]]-types and [[addressing mode]]s, as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below). <center> {| class="wikitable" style="text-align: center; width: 100px; height: 50px;" |+ Execution times for typical instructions<br/>(in clock cycles)<ref>{{cite book|title=[[MASM|Microsoft Macro Assembler]] 5.0 Reference Manual|year=1987|publisher=Microsoft Corporation| quote=Timings and encodings in this manual are used with permission of Intel and come from the following publications: Intel Corporation. iAPX 86, 88, 186 and 188 User's Manual, Programmer's Reference, Santa Clara, Calif. 1986.}} (Similarly for iAPX 286, 80386, 80387.) </ref>{{page number|date=December 2010}} |- style="vertical-align:bottom; border-bottom:3px double #999;" !align=left | instruction !align=left | register-register !align=left | register immediate !align=left | register-memory !align=left | memory-register !align=left | memory-immediate |- style="vertical-align:top; border-bottom:1px solid #999;" |mov || 2 || 4|| 8+EA || 9+EA || 10+EA |- style="vertical-align:top; border-bottom:1px solid #999;" |ALU || 3 ||4|| 9+EA, || 16+EA,|| 17+EA |- style="vertical-align:top; border-bottom:1px solid #999;" |jump || colspan="5" | ''register'' => 11 ; ''label'' => 15 ; ''condition,label'' => 16 |- style="vertical-align:top; border-bottom:1px solid #999;" |integer multiply || colspan="5" | 70~160 (depending on operand ''data'' as well as size) plus EA |- style="vertical-align:top; border-bottom:1px solid #999;" |signed integer divide || colspan="5" | 80~190 (depending on operand ''data'' as well as size) plus EA |}</center> *EA = time to compute effective address, ranging from 5 to 12 cycles. *Timings are best case, depending on prefetch status, instruction alignment, and other factors. [[Image:Intel 8086 block scheme.svg|thumb|405px|''Simplified block diagram over Intel 8088 (a variant of 8086); 1=main registers; 2=segment registers and IP; 3=address adder; 4=internal address bus; 5=instruction queue; 6=control unit (very simplified!); 7=bus interface; 8=internal databus; 9=ALU; 10/11/12=external address/data/control bus.'']] As can be seen from these tables, operations on registers and immediates were fast (between 2 and 4 cycles), while memory-operand instructions and jumps were quite slow; jumps took more cycles than on the simple [[Intel 8080|8080]] and [[Intel 8085|8085]], and the 8088 (used in the IBM PC) was additionally hampered by its narrower bus. The reasons why most memory related instructions were slow were threefold: *Loosely-coupled fetch and execution units are efficient for instruction prefetch, but not for jumps and random data access (without special measures). *No dedicated address calculation adder was afforded; the microcode routines had to use the main ALU for this (although there was a dedicated ''segment'' + ''offset'' adder). *The address and data buses were [[multiplexing|multiplex]]ed, forcing a slightly longer (33~50%) bus cycle than in typical contemporary 8-bit processors. However, memory access performance was drastically enhanced with Intel's next generation chips. The [[Intel 80186|80186]] and [[Intel 80286|80286]] both had dedicated address calculation hardware, saving many cycles, and the 80286 also had separate (non-multiplexed) address and data buses. ===Floating point=== The 8086/8088 could be connected to a mathematical coprocessor to add hardware/microcode-based [[floating point]] performance. The [[Intel 8087]] was the standard math coprocessor for the 8086 and 8088, operating on 80-bit numbers. Manufacturers like [[Cyrix]] (8087-compatible) and [[Weitek]] (''non'' 8087-compatible) eventually came up with high performance floating point co-processors that competed with the 8087 as well as with the subsequent, higher performing [[Intel 80387]]. ==Chip versions== The clock frequency was originally limited to 5&nbsp;MHz (IBM PC used 4.77&nbsp;MHz, 4/3 the standard NTSC [[color burst]] frequency), but the last versions in [[HMOS]] were specified for 10&nbsp;MHz. HMOS-III and [[CMOS]] versions were manufactured for a long time (at least a while into the 1990s) for [[embedded system]]s, although its successor, the [[Intel 80186|80186]]/[[Intel 80188|80188]] (which includes some on-chip peripherals), has been more popular for embedded use. ===Derivatives and clones=== [[Image:KL USSR KP1810BM86.jpg|right|thumb|180px|Soviet clone KP1810BM86.]] [[Image:Oki 80c86a.jpg|thumb|right|180px|[[Oki Electric Industry|OKI]] M80C86A [[QFP|QFP-56]].]] Compatible—and, in many cases, enhanced—versions were manufactured by [[Fujitsu]], [[Harris Corporation|Harris]]/[[Intersil]], [[Oki Electric Industry|OKI]], [[Siemens AG]], [[Texas Instruments]], [[NEC]], [[Mitsubishi]], and [[AMD]]. For example, the [[NEC V20]] and NEC V30 pair were hardware compatible with the 8088 and 8086, respectively, but incorporated the instruction set of the 80186 along with some (but not all) of the 80186 speed enhancements, providing a drop-in capability to upgrade both instruction set and processing speed without manufacturers having to modify their designs. Such relatively simple and low-power 8086-compatible processors in CMOS are still used in embedded systems. The electronics industry of the [[Soviet Union]] was able to replicate the 8086 through both [[industrial espionage]] and reverse engineering. The resulting chip, [[K1810BM86]], was binary and pin-compatible with the 8086, but was not mechanically compatible because it used metric measurements. The 8088 and 8086 were the respective cores of the Soviet-made PC-compatible [[ES1840]] and [[ES1841]] desktops. However, these computers had significant hardware differences from their authentic prototypes, and the data/address bus circuitry was designed independently of Intel products.{{verify source|date=July 2011}} ES1841 was the first PC compatible computer with dynamic bus sizing (US Pat. No 4,831,514). Later some of the ES1841 principles were adopted in PS/2 (US Pat. No 5,548,786) and some other machines (UK Patent Application, Publication No. GB-A-2211325, Published June. 28, 1989). ==Microcomputers using the 8086== *The first commercial microcomputer built on the basis of the 8086 was the [[Mycron]] 2000. *One of the most influential microcomputers of all, the [[IBM PC]], used the [[Intel 8088]], a version of the 8086 with an eight-bit [[data bus]] (as mentioned above). *The first [[Compaq Deskpro]] used an 8086 running at 7.14&nbsp;MHz, (?) but was capable of running add-in cards designed for the 4.77&nbsp;MHz [[IBM PC XT]]. *An 8 MHz 8086 was used in the [[Olivetti M24|AT&T 6300 PC]] (built by [[Olivetti]]), an IBM PC-compatible office desktop microcomputer. The M24 / PC 6300 has IBM PC/XT compatible 8-bit expansion slots, but some of them have a proprietary extension providing the full 16-bit data bus of the 8086 CPU (similar in concept to the 16-bit slots of the [[IBM PC AT]], but different in the design details). *The [[IBM Personal System/2|IBM PS/2]] models 25 and 30 were built with an 8&nbsp;MHz 8086. *The Amstrad [[PC-1512|PC1512]], PC1640, PC2086, PC3086 and PC5086 all used 8086 CPUs at 8&nbsp;MHz. * The [[NEC PC-9801]]. *The [[Tandy 1000]] SL-series machines used 8086 CPUs. *The [[IBM Displaywriter]] word processing machine<ref name = "InfoWorld Aug 1982">{{cite journal | last = Zachmann | first = Mark| title = Flaws in IBM Personal Computer frustrate critic | journal = InfoWorld | volume = 4 | issue = 33 | pages = pp. 57-58 | publisher = Popular Computing | location = Palo Alto, CA | date = August 23, 1982| url = http://books.google.com/books?id=VDAEAAAAMBAJ&pg=PA57| issn = 0199-6649| quote = the IBM Displaywriter is noticeably more expensive than other industrial micros that use the 8086.}}</ref> and the Wang Professional Computer, manufactured by [[Wang Laboratories]], also used the 8086. *[[NASA]] used original 8086 CPUs on equipment for ground-based maintenance of the [[Space Shuttle Discovery]] until the end of the space shuttle program in 2011. This decision was made to prevent [[software regression]] that might result from upgrading or from switching to imperfect clones.<ref>[http://www.nytimes.com/2002/05/12/technology/ebusiness/12NASA.html?pagewanted=2 For Old Parts, NASA Boldly Goes ... on eBay], May 12, 2002</ref> ==See also== *[[x86 architecture]] ==Notes and references== {{Reflist|2}} ==External links== *[http://datasheets.chipdb.org/Intel/x86/808x/datashts/8086 Intel datasheets] *[http://www.cpu-world.com/CPUs/8086/ List of 8086 CPUs and their clones at CPUworld.com] *[http://www.cpu-world.com/info/Pinouts/8086.html 8086 Pinouts] {{Intel processors|discontinued}} [[Category:1978 introductions]] [[Category:Intel x86 microprocessors|8086]] [[ar:إنتل 8086]] [[bg:Intel 8086]] [[bs:Intel 8086]] [[ca:Intel 8086]] [[cs:Intel 8086]] [[de:Intel 8086]] [[et:Intel 8086]] [[el:Intel 8086]] [[es:Intel 8086 y 8088]] [[fr:Intel 8086]] [[ko:인텔 8086]] [[hr:Intel 8086]] [[id:Intel 8086]] [[it:Intel 8086]] [[he:8086 (מעבד)]] [[hu:Intel 8086]] [[ml:ഇന്റൽ 8086]] [[ms:Intel 8086]] [[nl:Intel 8086]] [[ja:Intel 8086]] [[no:Intel 8086]] [[pl:Intel 8086]] [[pt:Intel 8086]] [[ro:Intel 8086]] [[ru:Intel 8086]] [[sk:Intel 8086]] [[sr:Intel 8086]] [[fi:Intel 8086]] [[sv:Intel 8086]] [[tr:Intel 8086]] [[uk:Intel 8086]] [[zh:Intel 8086]]'
Whether or not the change was made through a Tor exit node (tor_exit_node)
0
Unix timestamp of change (timestamp)
1336729638