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* 240-pin DIMM, used for DDR2 SDRAM, DDR3 SDRAM and ] DRAM * 240-pin DIMM, used for DDR2 SDRAM, DDR3 SDRAM and ] DRAM
* 244-pin MiniDIMM, used for DDR2 SDRAM * 244-pin MiniDIMM, used for DDR2 SDRAM
* 284-pin DIMM, used for ] SDRAM * 260-pin SO-DIMM, used for ] SDRAM
* 288-pin DIMM, used for DDR4 SDRAM


== 168-pin SDRAM == == 168-pin SDRAM ==
Line 31: Line 32:
== DDR DIMMs == == DDR DIMMs ==


], ] and ] all have different pin counts, and different notch positions. As of February 2014, DDR3 SDRAM is a modern type of dynamic random access memory (DRAM) with a high-bandwidth ("double data rate") interface, and has been in use since 2007. It is the higher-speed successor to DDR and DDR2, and predecessor to ] synchronous dynamic random access memory (SDRAM) chips. DDR3 SDRAM is neither forward nor backward compatible with any earlier type of random access memory (RAM) because of different signalling voltages, timings, and other factors. ], ], ] and ] all have different pin counts, and different notch positions. As of August, 2014, DDR4 SDRAM is a modern type of dynamic random access memory (DRAM) with a high-bandwidth ("double data rate") interface, and has been in use since 2013. It is the higher-speed successor to DDR2 and DDR3. DDR4 SDRAM is neither forward nor backward compatible with any earlier type of random access memory (RAM) because of different signalling voltages, timings, as well as other differing factors between the technologies and their implementation.


== SPD EEPROM == == SPD EEPROM ==
Line 60: Line 61:


; ] DIMMs ; ] DIMMs
: These first synchronous registered DRAM DIMMs had the same bus frequency for data, address and control lines. : DIMMs based on Single Data Rate (SDR) DRAM had the same bus frequency for data, address and control lines.
:* PC66 = 66 MHz
:* PC100 = 100 MHz
:* PC133 = 133 MHz


{| class="wikitable"
|- class="hintergrundfarbe6"
!Chip !! Module !! Effective Clock !! Voltage
|-
|SDR-66 || PC-66 || 66 MHz || 3.3 V
|-
|SDR-100 || PC-100 || 100 MHz || 3.3 V
|-
|SDR-133 || PC-133 || 133 MHz || 3.3 V
|}
; ] (DDR1) DIMMs ; ] (DDR1) DIMMs
: DIMMs based on Double Data Rate (DDR) DRAM have data but not the strobe at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. : DIMMs based on Double Data Rate (DDR) DRAM had data but not the strobe at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes.

:* PC1600 = 200 MHz data & strobe / 100 MHz clock for address and control
{| class="wikitable"
:* PC2100 = 266 MHz data & strobe / 133 MHz clock for address and control
|- class="hintergrundfarbe6"
:* PC2700 = 333 MHz data & strobe / 166 MHz clock for address and control
!Chip !! Module !! Memory Clock !! I/O Clock !! Effective Clock !! Voltage
:* PC3200 = 400 MHz data & strobe / 200 MHz clock for address and control
|-
|DDR-200 || PC-1600 || 100 MHz || 100 MHz || 200 MHz || 2.5 V
|-
|DDR-266 || PC-2100 || 133 MHz || 133 MHz || 266 MHz || 2.5 V
|-
|DDR-333 || PC-2700 || 166 MHz || 166 MHz || 333 MHz || 2.5 V
|-
|DDR-400 || PC-3200 || 200 MHz || 200 MHz || 400 MHz || 2.5 V
|}


; ] DIMMs ; ] DIMMs
: DIMMs based on Double Data Rate 2 (DDR2) DRAM also have data and data strobe frequencies at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. The power consumption and voltage of DDR2 is significantly lower than DDR(1) at the same speed. : DIMMs based on Double Data Rate 2 (DDR2) DRAM also had data and strobe frequencies at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. The power consumption and voltage of DDR2 is significantly lower than DDR(1) at the same speed.

:* PC2-3200 = 400 MHz data & strobe / 200 MHz clock for address and control
{| class="wikitable"
:* PC2-4200 = 533 MHz data & strobe / 266 MHz clock for address and control
|- class="hintergrundfarbe6"
:* PC2-5300 = 667 MHz data & strobe / 333 MHz clock for address and control
!Chip !! Module !! Memory Clock !! I/O Clock !! Effective Clock !! Voltage
:* PC2-6400 = 800 MHz data & strobe / 400 MHz clock for address and control
|-
:* PC2-8500 = 1066 MHz data & strobe / 533 MHz clock for address and control
|DDR2-400 || PC2-3200 || 100 MHz || 200 MHz || 400 MHz || 1.8 V
|-
|DDR2-533 || PC2-4200 || 133 MHz || 266 MHz || 533 MHz || 1.8 V
|-
|DDR2-667 || PC2-5300 || 166 MHz || 333 MHz || 667 MHz || 1.8 V
|-
|DDR2-800 || PC2-6400 || 200 MHz || 400 MHz || 800 MHz || 1.8 V
|-
|DDR2-1066 || PC2-8500 || 266 MHz || 533 MHz || 1066 MHz || 1.8 V
|}


; ] DIMMs ; ] DIMMs
: DIMMs based on Double Data Rate 3 (DDR3) DRAM have data and strobe frequencies at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. The power consumption and voltage of DDR3 is lower than DDR2 of the same speed. : DIMMs based on Double Data Rate 3 (DDR3) DRAM have data and strobe frequencies at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. The power consumption and voltage of DDR3 is lower than DDR2 of the same speed.

:* PC3-6400 = 800 MHz data & strobe / 400 MHz clock for address and control
{| class="wikitable"
:* PC3-8500 = 1066 MHz data & strobe / 533 MHz clock for address and control
|- class="hintergrundfarbe6"
:* PC3-10600 = 1333 MHz data & strobe / 667 MHz clock for address and control
!Chip !! Module !! Memory Clock !! I/O Clock !! Effective Clock !! Voltage
:* PC3-12800 = 1600 MHz data & strobe / 800 MHz clock for address and control
|-
:* PC3-14900 = 1866 MHz data & strobe / 933 MHz clock for address and control
:* PC3-17000 = 2133 MHz data & strobe / 1066 MHz clock for address and control |DDR3-800 || PC3-6400 || 100 MHz || 400 MHz || 800 MHz || 1.5 V
|-
|DDR3-1066 || PC3-8500 || 133 MHz || 533 MHz || 1066 MHz || 1.5 V
|-
|DDR3-1333 || PC3-10600 || 166 MHz || 667 MHz || 1333 MHz || 1.5 V
|-
|DDR3-1600 || PC3-12800 || 200 MHz || 800 MHz || 1600 MHz || 1.5 V
|-
|DDR3-1866 || PC3-14900 || 233 MHz || 933 MHz || 1866 MHz || 1.5 V
|-
|DDR3-2133 || PC3-17000 || 266 MHz || 1066 MHz || 2133 MHz || 1.5 V
|}

; ] DIMMs
: DIMMs based on Double Data Rate 4 (DDR4) DRAM have data and strobe frequencies at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. The power consumption and voltage of DDR4 is lower than DDR3 of the same speed.

{| class="wikitable"
|- class="hintergrundfarbe6"
!Chip !! Module !! Memory Clock !! I/O Clock !! Effective Clock !! Voltage
|-
|DDR4-1600 || PC4-12800 || 200 MHz || 800 MHz || 1600 MHz || 1.2 V
|-
|DDR4-1866 || PC4-14900 || 233 MHz || 933 MHz || 1866 MHz || 1.2 V
|-
|DDR4-2133 || PC4-17000 || 266 MHz || 1066 MHz || 2133 MHz || 1.2 V
|-
|DDR4-2400 || PC4-19200 || 300 MHz || 1200 MHz || 2400 MHz || 1.2 V
|-
|DDR4-2666 || PC4-21300 || 333 MHz || 1333 MHz || 2666 MHz || 1.2 V
|-
|DDR4-3200 || PC4-25600 || 400 MHz || 1600 MHz || 3200 MHz || 1.2 V
|}


== Form factors == == Form factors ==
Several form factors are commonly used in DIMMs. Single Data Rate Synchronous DRAM (SDR SDRAM) DIMMs were primarily manufactured in {{convert|1.5|in|mm}} and {{convert|1.7|in|mm}} heights. When ] servers started becoming popular, these form factor registered DIMMs had to plug into angled DIMM sockets to fit in the {{convert|1.75|in|mm}} high box. To alleviate this issue, the next standards of DDR DIMMs were created with a "low profile" (LP) height of around {{convert|1.2|in|mm}}. These fit into vertical DIMM sockets for a 1U platform. Several form factors are commonly used in DIMMs. Single Data Rate Synchronous DRAM (SDR SDRAM) DIMMs were primarily manufactured in {{convert|1.5|in|mm}} and {{convert|1.7|in|mm}} heights. When ] servers started becoming popular, these form factor registered DIMMs had to plug into angled DIMM sockets to fit in the {{convert|1.75|in|mm}} high box. To alleviate this issue, the next standards of DDR DIMMs were created with a "low profile" (LP) height of around {{convert|1.2|in|mm}}. These fit into vertical DIMM sockets for a 1U platform.


With the advent of blade servers, angled slots have once again become common in order to accommodate LP form factor DIMMs in these space-constrained boxes. This led to the development of the Very Low Profile (VLP) form factor DIMM with a height of around {{convert|0.72|in|mm}}. The DDR3 JEDEC standard for VLP DIMM height is around {{convert|0.74|in|mm}}. These will fit vertically in ] systems. With the advent of blade servers, angled slots have once again become common in order to accommodate LP form factor DIMMs in these space-constrained boxes. This led to the development of the Very Low Profile (VLP) form factor DIMM with a height of around {{convert|0.72|in|mm}}. The DDR3 JEDEC standard for VLP DIMM height is around {{convert|0.740|in|mm}}. These will fit vertically in ] systems.

Full-height 240-pin DDR2 and DDR3 DIMMs are all specified at a height of around {{convert|1.18|in|mm}} by standards set by JEDEC. These form factors include 240-pin DIMM, SODIMM, Mini-DIMM and Micro-DIMM.<ref>, accessed Aug. 20, 2014.</ref>


Full-height DDR2 and DDR3 DIMMs are all specified at a height of around {{convert|1.18|in|mm}} by standards set by JEDEC. These form factors include 240-pin DIMM, SODIMM, Mini-DIMM and Micro-DIMM.<ref>. accessed Aug. 8, 2014.</ref><ref>, accessed Aug. 8, 2014.</ref><ref>, accessed Aug. 9, 2014.</ref> Full-height 288-pin DDR4 DIMMs are slightly taller than their DDR3 counterparts at {{convert|1.23|in|mm}}. Similarly, VLP DDR4 DIMMs are also marginally taller than their DDR3 equivalent at nearly {{convert|0.74|in|mm}}.<ref>, accessed Aug. 20, 2014.</ref>


== See also == == See also ==

Revision as of 13:25, 21 August 2014

Two types of DIMMs: a 168-pin SDRAM module (top) and a 184-pin DDR SDRAM module (bottom). Note that the SDRAM module has two notches (rectangular cut or incision) on the bottom edge, while the DDR1 SDRAM module has only one. Also note that both modules have 8 RAM chips, but the lower one has an unoccupied space for a 9th.
3 SDRAM DIMM slots

A DIMM or dual in-line memory module comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers. DIMMs began to replace SIMMs (single in-line memory modules) as the predominant type of memory module as Intel P5-based Pentium processors began to gain market share.

While the contacts on SIMMs on both sides are redundant, DIMMs have separate electrical contacts on each side of the module. Another difference is that standard SIMMs have a 32-bit data path, while standard DIMMs have a 64-bit data path. Since Intel's Pentium, many processors have a 64-bit bus width, requiring SIMMs installed in matched pairs in order to populate the data bus. The processor would then access the two SIMMs in parallel. DIMMs were introduced to eliminate this practice.

The most common types of DIMMs are:

  • 72-pin SO-DIMM (not the same as a 72-pin SIMM), used for FPM DRAM and EDO DRAM
  • 100-pin DIMM, used for printer SDRAM
  • 144-pin SO-DIMM, used for SDR SDRAM
  • 168-pin DIMM, used for SDR SDRAM (less frequently for FPM/EDO DRAM in workstations/servers, may be 3.3 or 5 V)
  • 172-pin MicroDIMM, used for DDR SDRAM
  • 184-pin DIMM, used for DDR SDRAM
  • 200-pin SO-DIMM, used for DDR SDRAM and DDR2 SDRAM
  • 204-pin SO-DIMM, used for DDR3 SDRAM
  • 214-pin MicroDIMM, used for DDR2 SDRAM
  • 240-pin DIMM, used for DDR2 SDRAM, DDR3 SDRAM and FB-DIMM DRAM
  • 244-pin MiniDIMM, used for DDR2 SDRAM
  • 260-pin SO-DIMM, used for DDR4 SDRAM
  • 288-pin DIMM, used for DDR4 SDRAM

168-pin SDRAM

Notch positions on DDR (top) and DDR2 (bottom) DIMM modules.

On the bottom edge of 168-pin DIMMs there are 2 notches, and the location of each notch determines a particular feature of the module.

  • The first notch is DRAM key position. It represents RFU (reserved future use), registered, and unbuffered (in that order from left to middle to right position).
  • The second notch is voltage key position. It represents 5.0 V, 3.3 V, and Reserved (order as above).
  • The upper DIMM in the (topmost) photo is an unbuffered 3.3 V 168-pin DIMM. Variants of DIMM slots support DDR, DDR2 and DDR3 RAM.

DDR DIMMs

DDR, DDR2, DDR3 and DDR4 all have different pin counts, and different notch positions. As of August, 2014, DDR4 SDRAM is a modern type of dynamic random access memory (DRAM) with a high-bandwidth ("double data rate") interface, and has been in use since 2013. It is the higher-speed successor to DDR2 and DDR3. DDR4 SDRAM is neither forward nor backward compatible with any earlier type of random access memory (RAM) because of different signalling voltages, timings, as well as other differing factors between the technologies and their implementation.

SPD EEPROM

A DIMM's capacity and other operational parameters may be identified with serial presence detect (SPD), an additional chip which contains information about the module type and timing for the memory controller to be configured correctly. The SPD EEPROM connects to the System Management Bus and may also contain thermal sensors (TS-on-DIMM).

Error correction

ECC DIMMs are those that have extra data bits which can be used by the system memory controller to detect and correct errors. There are numerous ECC schemes, but perhaps the most common is Single Error Correct, Double Error Detect (SECDED) which uses an extra byte per 64-bit word. ECC modules usually carry a multiple of 9 instead of a multiple of 8 chips.

Ranking

Main article: Memory rank

Sometimes memory modules are designed with two or more independent sets of DRAM chips connected to the same address and data buses; each such set is called a rank. Since all ranks share the same buses, only one rank may be accessed at any given time; it is specified by activating the corresponding rank's chip select (CS) signal. All other ranks are deactivated for the duration of the operation by having their corresponding CS signals deactivated. DIMMs are currently being commonly manufactured with up to four ranks per module. Consumer DIMM vendors have recently begun to distinguish between single and dual ranked DIMMs.

DIMMs are often referred to as "single-sided" or "double-sided" to describe whether the DRAM chips are located on one or both sides of the module's printed circuit board (PCB). However, these terms may cause confusion, as the physical layout of the chips does not necessarily relate to how they are logically organized or accessed.

JEDEC decided that the terms "dual-sided," "double-sided," or "dual-banked" were not correct when applied to registered DIMMs.

Organization

Most DIMMs are built using "×4" (by 4) memory chips or "×8" (by 8) memory chips with 9 chips per side. "×4" or "×8" refer to the data width of the DRAM chips in bits.

In the case of the "×4"-registered DIMMs, the data width per side is 36 bits; therefore, the memory controller (which requires 72 bits) needs to address both sides at the same time to read or write the data it needs. In this case, the two-sided module is single-ranked.

For "×8"-registered DIMMs, each side is 72 bits wide, so the memory controller only addresses one side at a time (the two-sided module is dual-ranked).

Note: The above example applies to ECC memory which stores 72 bits instead of the more common 64. There would also be one extra chip per group of eight which is not counted.

Speeds

For various technologies, there are certain bus and device clock frequencies that are standardized. There is also a decided nomenclature for each of these speeds for each type.

SDR SDRAM DIMMs
DIMMs based on Single Data Rate (SDR) DRAM had the same bus frequency for data, address and control lines.
Chip Module Effective Clock Voltage
SDR-66 PC-66 66 MHz 3.3 V
SDR-100 PC-100 100 MHz 3.3 V
SDR-133 PC-133 133 MHz 3.3 V
DDR SDRAM (DDR1) DIMMs
DIMMs based on Double Data Rate (DDR) DRAM had data but not the strobe at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes.
Chip Module Memory Clock I/O Clock Effective Clock Voltage
DDR-200 PC-1600 100 MHz 100 MHz 200 MHz 2.5 V
DDR-266 PC-2100 133 MHz 133 MHz 266 MHz 2.5 V
DDR-333 PC-2700 166 MHz 166 MHz 333 MHz 2.5 V
DDR-400 PC-3200 200 MHz 200 MHz 400 MHz 2.5 V
DDR2 SDRAM DIMMs
DIMMs based on Double Data Rate 2 (DDR2) DRAM also had data and strobe frequencies at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. The power consumption and voltage of DDR2 is significantly lower than DDR(1) at the same speed.
Chip Module Memory Clock I/O Clock Effective Clock Voltage
DDR2-400 PC2-3200 100 MHz 200 MHz 400 MHz 1.8 V
DDR2-533 PC2-4200 133 MHz 266 MHz 533 MHz 1.8 V
DDR2-667 PC2-5300 166 MHz 333 MHz 667 MHz 1.8 V
DDR2-800 PC2-6400 200 MHz 400 MHz 800 MHz 1.8 V
DDR2-1066 PC2-8500 266 MHz 533 MHz 1066 MHz 1.8 V
DDR3 SDRAM DIMMs
DIMMs based on Double Data Rate 3 (DDR3) DRAM have data and strobe frequencies at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. The power consumption and voltage of DDR3 is lower than DDR2 of the same speed.
Chip Module Memory Clock I/O Clock Effective Clock Voltage
DDR3-800 PC3-6400 100 MHz 400 MHz 800 MHz 1.5 V
DDR3-1066 PC3-8500 133 MHz 533 MHz 1066 MHz 1.5 V
DDR3-1333 PC3-10600 166 MHz 667 MHz 1333 MHz 1.5 V
DDR3-1600 PC3-12800 200 MHz 800 MHz 1600 MHz 1.5 V
DDR3-1866 PC3-14900 233 MHz 933 MHz 1866 MHz 1.5 V
DDR3-2133 PC3-17000 266 MHz 1066 MHz 2133 MHz 1.5 V
DDR4 SDRAM DIMMs
DIMMs based on Double Data Rate 4 (DDR4) DRAM have data and strobe frequencies at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. The power consumption and voltage of DDR4 is lower than DDR3 of the same speed.
Chip Module Memory Clock I/O Clock Effective Clock Voltage
DDR4-1600 PC4-12800 200 MHz 800 MHz 1600 MHz 1.2 V
DDR4-1866 PC4-14900 233 MHz 933 MHz 1866 MHz 1.2 V
DDR4-2133 PC4-17000 266 MHz 1066 MHz 2133 MHz 1.2 V
DDR4-2400 PC4-19200 300 MHz 1200 MHz 2400 MHz 1.2 V
DDR4-2666 PC4-21300 333 MHz 1333 MHz 2666 MHz 1.2 V
DDR4-3200 PC4-25600 400 MHz 1600 MHz 3200 MHz 1.2 V

Form factors

Several form factors are commonly used in DIMMs. Single Data Rate Synchronous DRAM (SDR SDRAM) DIMMs were primarily manufactured in 1.5 inches (38 mm) and 1.7 inches (43 mm) heights. When 1U rackmount servers started becoming popular, these form factor registered DIMMs had to plug into angled DIMM sockets to fit in the 1.75 inches (44 mm) high box. To alleviate this issue, the next standards of DDR DIMMs were created with a "low profile" (LP) height of around 1.2 inches (30 mm). These fit into vertical DIMM sockets for a 1U platform.

With the advent of blade servers, angled slots have once again become common in order to accommodate LP form factor DIMMs in these space-constrained boxes. This led to the development of the Very Low Profile (VLP) form factor DIMM with a height of around 0.72 inches (18 mm). The DDR3 JEDEC standard for VLP DIMM height is around 0.740 inches (18.8 mm). These will fit vertically in ATCA systems.

Full-height 240-pin DDR2 and DDR3 DIMMs are all specified at a height of around 1.18 inches (30 mm) by standards set by JEDEC. These form factors include 240-pin DIMM, SODIMM, Mini-DIMM and Micro-DIMM.

Full-height 288-pin DDR4 DIMMs are slightly taller than their DDR3 counterparts at 1.23 inches (31 mm). Similarly, VLP DDR4 DIMMs are also marginally taller than their DDR3 equivalent at nearly 0.74 inches (19 mm).

See also

References

  1. Temperature Sensor in DIMM memory modules
  2. JEDEC MO-269J Whitepaper., accessed Aug. 20, 2014.
  3. JEDEC MO-309E Whitepaper., accessed Aug. 20, 2014.

External links

Category: