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			{{Use American English\|date = March 2019}}
	'''PSoC''' is a family of ] arrays made by ], featuring a ] and integrated analog and digital peripherals.
			{{Short description\|Type of integrated circuit}}
			{{Use mdy dates\|date=October 2024}}
			]
			]
			]

			'''PSoC''' (programmable ]) is a family of ] ]s by ]. These chips include a ] core and ] arrays of configurable integrated analog and digital peripherals.
	PSoC is an acronym for "Programmable System-on-Chip".
	PSoC™ Functional Overview
	The PSoC™ family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pin-outs and packages.
	The PSoC architecture is comprised of four main areas: PSoC core, digital System, Analog System, and System Resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C29x66 family can have up to eight IO ports that connect to the global digital and analog interconnects, providing access to 16 digital blocks and 12 analog blocks.
	The PSoC Core
	The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 25 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT).
	Memory encompasses 32 KB of Flash for program storage, 2 KB of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection.
	The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate crystal- accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device.
	PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.
	PSoC Block diagram:

			== History ==

			In 2002, Cypress began shipping commercial quantities of the PSoC 1.<ref>Reuters: 2009</ref> To promote the PSoC, Cypress sponsored a "PSoC Design Challenge" in '']'' magazine in 2002 and 2004.<ref>Circuit Cellar: {{dead link\|date=July 2021\|bot=medic}}{{cbignore\|bot=medic}}</ref>

			In April 2013, Cypress released the fourth generation, PSoC 4. The PSoC 4 features a 32-bit ] CPU, with programmable analog blocks (]s and comparators), programmable digital blocks (]-based UDBs), programmable routing and flexible GPIO (route any function to any pin), a serial communication block (for SPI, UART, ]), a timer/counter/PWM block and more.<ref>{{cite web \|url=https://finance.yahoo.com/news/fully-qualified-production-silicon-cypress-120000787.html \|title=Fully Qualified Production Silicon for Cypress's First Two PSoC® 4 Product Families Is Now Available \|website=yahoo.com \|access-date=April 12, 2018}}</ref>
	The Digital System
	The Digital System is composed of 16 digital PSoC blocks.
	Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include those listed below.
	• PWMs (8 to 32 bit)
	• PWMs with Dead band (8 to 32 bit)
	• Counters (8 to 32 bit)
	• Timers (8 to 32 bit)
	• UART 8 bit with selectable parity (up to 4)
	• SPI master and slave (up to 4 each)
	• I2C slave and multi-master (1 available as a System Resource)
	• Cyclical Redundancy Checker/Generator (8 to 32 bit)
	• IrDA (up to 4)
	• Pseudo Random Sequence Generators (8 to 32 bit)
	The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application.
	The Analog System
	The Analog System is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are listed below.
	• Analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR)
	• Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch)
	• Amplifiers (up to 4, with selectable gain to 48x)
	• Instrumentation amplifiers (up to 2, with selectable gain to 93x)
	• Comparators (up to 4, with 16 selectable thresholds)
	• DACs (up to 4, with 6- to 9-bit resolution)
	• Multiplying DACs (up to 4, with 6- to 9-bit resolution)
	• High current output drivers (four with 40 mA drive as a Core resource)
	• 1.3V reference (as a System Resource)
	• DTMF Dialer
	• Modulators
	• Correlators
	• Peak Detectors
	• Many other topologies possible
	Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks.

			PSoC is used in devices as simple as Sonicare toothbrushes and Adidas sneakers, and as complex as the ] set-top box. One PSoC implements ] for the ] ] on the Apple ].{{Citation needed\|date=February 2022}}

			In 2014, Cypress extended the PSoC 4 family by integrating a ] radio along with a PSoC 4 Cortex-M0-based SoC in a single, monolithic die.

			In 2016, Cypress released PSoC 4 S-Series, featuring ] CPU.<ref>{{Cite press release \|url=http://www.prnewswire.com/news-releases/cypress-offers-complete-portfolio-of-flexible-psoc-arm-cortex-m0-and-cortex-m0-solutions-to-replace-legacy-8-bit-and-16-bit-platforms-300224302.html \|title=Cypress Offers Complete Portfolio of Flexible PSoC ARM Cortex-M0 and Cortex-M0+ Solutions to Replace Legacy 8-Bit and 16-Bit Platforms \|last=Corp. \|first=Cypress Semiconductor \|website=www.prnewswire.com \|access-date=March 4, 2016}}</ref>


	Digital system Block diagram Analog system Block diagram

			== Overview ==
			A PSoC integrated circuit is composed of a core, configurable analog and digital blocks, and programmable routing and interconnect. The configurable blocks in a PSoC are the biggest difference from other microcontrollers.

			PSoC has three separate memory spaces: paged SRAM for data, ] for instructions and fixed data, and I/O registers for controlling and accessing the configurable logic blocks and functions. The device is created using ] technology.
	{{Microcompu-stub}}

			PSoC resembles an ]: blocks can be assigned a wide range of functions and interconnected on-chip. Unlike an ASIC, there is no special manufacturing process required to create the custom configuration – only startup code that is created by Cypress' ''PSoC Designer'' (for PSoC 1) or ''PSoC Creator'' (for PSoC 3 / 4 / 5) ].

			PSoC resembles an ] in that at power up it must be configured, but this configuration occurs by loading instructions from the built-in Flash memory.

			PSoC most closely resembles a ] combined with a PLD and programmable analog. Code is executed to interact with the user-specified peripheral functions (called "Components"), using automatically generated APIs and interrupt routines. ''PSoC Designer'' or ''PSoC Creator'' generate the startup configuration code. Both integrate APIs that initialize the user selected components upon the users needs in a ]-like GUI.

			=== Configurable analog and digital blocks ===
			]

			Using configurable analog and digital blocks, designers can create and change mixed-signal embedded applications. The digital blocks are state machines that are configured using the blocks registers. There are two types of digital blocks, Digital Building Blocks (DBBxx) and Digital Communication Blocks (DCBxx). Only the communication blocks can contain serial I/O user modules, such as SPI, UART, etc.

			Each digital block is considered an 8-bit resource that designers can configure using pre-built digital functions or user modules (UM), or, by combining blocks, turn them into 16-, 24-, or 32-bit resources. Concatenating UMs together is how 16-bit PWMs and timers are created.

			There are two types of analog blocks. The continuous time (CT) blocks are composed of an op-amp circuit and designated as ACBxx where xx is 00–03. The other type is the switch cap (SC) blocks, which allow complex analog signal flows and are designated by ASCxy where x is the row and y is the column of the analog block. Designers can modify and personalize each module to any design.

			=== Programmable routing and interconnect ===
			PSoC mixed-signal arrays' flexible routing allows designers to route signals to and from I/O pins more freely than with many competing microcontrollers. Global buses allow for signal multiplexing and for performing logic operations. Cypress suggests that this allows designers to configure a design and make improvements more easily and faster and with fewer PCB redesigns than a digital logic gate approach or competing microcontrollers with more fixed function pins.

			== Series ==
			There are five different families of devices, each based around a different microcontroller core:
			* PSoC 1 – CY8C2xxxx series – M8C core.
			* PSoC 3 – CY8C3xxxx series – ] core.
			* PSoC 4 – CY8C4xxxx series – ] core.<ref>{{cite web \|url=http://electronicdesign.com/microcontrollers/custom-peripherals-surround-cortex-m0-platform \|title=Custom Peripherals Surround Cortex-M0 Platform \|date=April 16, 2013}}</ref>
			* PSoC 5/5LP – CY8C5xxxx series – ] core.
			* PSoC 6 – CY8C6xxxx series – ] core with an added ] core (in some models).<ref>{{cite web \|url=https://www.digikey.com/en/product-highlight/c/cypress/psoc-6-cy8ckit-062-pioneer-kit \|title=PSoC 6 CY8CKIT-062 Pioneer Kit – Cypress – DigiKey \|website=www.digikey.com \|access-date=April 12, 2018}}</ref>

			'''Bluetooth Low Energy'''

			Starting in 2014, Cypress began offering PSoC 4 BLE devices with integrated Bluetooth Low Energy (Bluetooth Smart). This can be used to create connected products leveraging the analog and digital blocks.<ref>{{cite web \|title=PSoC® 4 BLE (Bluetooth Smart) \|url=http://www.cypress.com/psoc4ble/ \|access-date=February 12, 2015}}</ref> Users can add and configure the BLE module directly in PSoC creator. Cypress also provides a complete Bluetooth Low Energy stack licensed from ] with both Peripheral and Central functionality.<ref>{{cite web \|title=Cypress offering BLE chipset, Here's what you need to know \|url=http://www.argenox.com/blog/cypress-offers-ble-chipset/ \|access-date=February 12, 2015}}</ref> The PSoC 6 series includes versions with BLE including ] features including extended range or higher speed.

			=== Summary ===
			{\| class="wikitable" style="margin:1em auto;"
			\|-
			! scope="col" \| PSoC 1
			! scope="col" \| PSoC 3
			! scope="col" \| PSoC 4
			! scope="col" \| PSoC 5/5LP
			! scope="col" \| PSoC 6
			\|-
			\| 8-bit M8C core<br /> up to 24 MHz, 4 MIPS
			\| 8-bit 8051 core (single-cycle)<br /> up to 67 MHz, 33 MIPS
			\| 32-bit ]<br /> up to 48 MHz, ? MIPS
			\| 32-bit ]<br /> up to 80 MHz, 84 MIPS
			\| 32-bit ] (up to 150 MHz)<br />32-bit ] (opt. up to 100 MHz)
			\|-
			\| Flash: 4 KB to 32 KB<br /> SRAM: 256 bytes to 2 KB
			\| Flash: 8 KB to 64 KB<br /> SRAM: 3 KB to 8 KB
			\| Flash: 16 KB to 256 KB<br /> SRAM: 2 KB to 32 KB
			\| Flash: 32 KB to 256 KB<br /> SRAM: 8 KB to 64 KB
			\| Flash: 512 KB to 2048 KB<br /> SRAM: 128 KB to 512 KB<br />expandable using quad SPI
			\|-
			\| I²C, SPI, UART,<br /> FS USB 2.0
			\| I²C, SPI, UART, LIN,<br /> FS USB 2.0, I²S, CAN
			\| I²C, SPI, UART, CAN<br /> .
			\| I²C, SPI, UART, LIN, CAN,
			FS USB 2.0, I²S
			\| I²C, SPI, UART, LIN, BLE (opt.), FS USB 2.0 (opt. host & device)
			\|-
			\| 16 digital PSoC blocks
			\| 16 to 24 UDBs (Universal Digital Blocks)
			\| 4 to 8 UDBs
			\| 20 to 24 UDBs
			\| 0 to 12 UDBs
			\|-
			\| 1 Delta-Sigma ADC (6 to 14-bit)
			131 ksps @ 8-bit;

			1 Sigma-Delta ADC (for capacitive sensing)

			Up to two DACs (6 to 8-bit)
			\| 1 Delta-Sigma ADC (8 to 20-bit)
			192 ksps @ 12-bit;

			Up to four DACs (8-bit)
			\| 1 SAR ADC (12-bit)

			1 Msps @ 12-bit;

			Up to two DACs (7 to 8-bit)

			\| 1 Delta-Sigma ADC (8 to 20-bit)

			192 ksps @12-bit;

			2 SAR ADCs (12-bit)

			1 Msps @ 12-bit;

			Up to four DACs (8-bit)
			\| 1 SAR ADC (12-bit) 1 MSPS

			1 12 Bit Voltage Mode DAC
			\|-
			\| Up to 64 I/O
			\| Up to 72 I/O
			\| Up to 98 I/O
			\| Up to 72 I/O
			\| Up to 104 I/O
			\|-
			\| Operation: 1.7 V to 5.25 V<br /> Active: 2 mA,<br /> Sleep: 3 μA<br /> Hibernate: ?
			\| Operation: 0.5 V to 5.5 V<br /> Active: 1.2 mA,<br /> Sleep: 1 μA,<br /> Hibernate: 200 nA
			\| Operation: 1.71 V to 5.5 V<br /> Active: 1.6 mA,<br /> Sleep: 1.3 μA,<br /> Hibernate: 150 nA
			\| Operation: 2.7 V to 5.5 V<br /> Active: 2 mA,<br /> Sleep: 2 μA,<br /> Hibernate: 300 nA
			\|
			\|-
			\| Requires ICE Cube and FlexPods
			\|
			\| On-chip SWD, Debug
			\| On-chip JTAG, SWD, SWV,<br /> Debug, Trace
			\|
			\|-
			\| CY8CKIT-001 Development Kit
			\| CY8CKIT-001 Development Kit<br /> CY8CKIT-030 Development Kit
			\| CY8CKIT-040 4000 Pioneer Kit<br />CY8CKIT-042 4200 Pioneer Kit
			CY8CKIT-043 4200M Prototyping Kit

			CY8CKIT-044 4200M Pioneer Kit

			CY8CKIT-046 4200L Pioneer Kit<br />CY8CKIT-049 4100 Prototype Kit
			\| CY8CKIT-001 Development Kit<br /> CY8CKIT-050 Development Kit<br /> CY8CKIT-059 Prototype Kit
			\| CY8CKIT-062-BLE Pioneer Kit
			\|}

			== Development tools ==

			=== PSoC Designer ===
			This is the first generation software IDE to design and debug and program the PSoC 1 devices. It introduced unique features including a library of pre-characterized analog and digital peripherals in a drag-and-drop design environment which could then be customized to specific design needs by leveraging the dynamically generated API libraries of code.

			=== PSoC Creator ===
			PSoC Creator is the second generation software IDE to design debug and program the PSoC 3 / 4 / 5 devices. The development IDE is combined with an easy-to-use graphical design editor to form a powerful hardware/software co-design environment. PSoC Creator consists of two basic building blocks. The program allows the user to select, configure and connect existing circuits on the chip and the components which are the equivalent of peripherals on MCUs. What makes PSoC intriguing is the possibility of creating its own application-specific peripherals in hardware. Cypress publishes component packs several times a year. PSoC users get new peripherals for their existing hardware without being charged or having to buy new hardware. PSoC Creator also allows much freedom in the assignment of peripherals to I/O pins.

			=== Cortex-M ===
			{{Main\|List of ARM Cortex-M development tools}}
			Generic ARM development tools for PSoC 4 and PSoC 5.

			== Documentation ==
			'''PSoC 4 / 5'''

			The amount of documentation for all ARM chips is daunting, especially for newcomers. The documentation for microcontrollers from past decades would easily be inclusive in a single document, but as chips have evolved so has the documentation grown. The total documentation is especially hard to grasp for all ARM chips since it consists of documents from the IC manufacturer (]) and documents from CPU core vendor (]).

			A typical top-down documentation tree is: manufacturer website, manufacturer marketing slides, manufacturer datasheet for the exact physical chip, manufacturer detailed reference manual that describes common peripherals and aspects of a physical chip family, ARM core generic user guide, ARM core technical reference manual, ARM architecture reference manual that describes the instruction set(s).

			;PSoC 4 / 5 documentation tree (top to bottom):
			# PSoC website.
			# PSoC marketing slides.
			# PSoC datasheet.
			# PSoC reference manuals.
			# ARM core website.
			# ARM core generic user guide.
			# ARM core technical reference manual.
			# ARM architecture reference manual.

			Cypress Semiconductor has additional documents, such as: evaluation board user manuals, application notes, getting started guides, software library documents, errata, and more. See ] section for links to official PSoC and ARM documents.

			== See also ==
			{{Portal\|Electronics}}
			* ], ], ]
			* ]s
			* ]
			* ], ], ]
			* ]
			* ], (])
			* ]
			* ]

			== References ==
			{{Reflist}}

			== Further reading ==
			{{See also\|ARM Cortex-M#Further reading\|l1=List of books about ARM Cortex-M}}

			== External links ==
			{{Commons category\|Cypress PSoC}}
			{{Wikibooks\|Embedded Systems/Cypress PSoC Microcontroller}}

			'''PSoC Official Documents'''
			* {{Official website\|http://www.cypress.com/psoc\|PSoC official website}}
			** for PSoC 1 family
			** for PSoC 3 / 4 / 5LP families
			** for PSoC 1 / 3 / 4 / 5LP families

			'''ARM Official Documents for PSoC 4 / 5'''
			{{Main\|ARM Cortex-M#External links\|l1=ARM Cortex-M external links}}

			'''Other'''
			* {{usurped\|1=}}
			*
			* El primer web site en Español sobre Microcontroladore Psoc

			{{System on a chip}}
			{{Embedded ARM-based chips}}
			{{Microcontrollers}}

			{{DEFAULTSORT:Psoc}}
			]
			]

Latest revision as of 23:33, 20 December 2024

Type of integrated circuit

PSoC 1 capacitive sensing development board with MiniProg programmer / debugger

PSoC (programmable system on a chip) is a family of microcontroller integrated circuits by Cypress Semiconductor. These chips include a CPU core and mixed-signal arrays of configurable integrated analog and digital peripherals.

History

In 2002, Cypress began shipping commercial quantities of the PSoC 1. To promote the PSoC, Cypress sponsored a "PSoC Design Challenge" in Circuit Cellar magazine in 2002 and 2004.

In April 2013, Cypress released the fourth generation, PSoC 4. The PSoC 4 features a 32-bit ARM Cortex-M0 CPU, with programmable analog blocks (operational amplifiers and comparators), programmable digital blocks (PLD-based UDBs), programmable routing and flexible GPIO (route any function to any pin), a serial communication block (for SPI, UART, I²C), a timer/counter/PWM block and more.

PSoC is used in devices as simple as Sonicare toothbrushes and Adidas sneakers, and as complex as the TiVo set-top box. One PSoC implements capacitive sensing for the touch-sensitive scroll wheel on the Apple iPod click wheel.

In 2014, Cypress extended the PSoC 4 family by integrating a Bluetooth Low Energy radio along with a PSoC 4 Cortex-M0-based SoC in a single, monolithic die.

In 2016, Cypress released PSoC 4 S-Series, featuring ARM Cortex-M0+ CPU.

Overview

A PSoC integrated circuit is composed of a core, configurable analog and digital blocks, and programmable routing and interconnect. The configurable blocks in a PSoC are the biggest difference from other microcontrollers.

PSoC has three separate memory spaces: paged SRAM for data, Flash memory for instructions and fixed data, and I/O registers for controlling and accessing the configurable logic blocks and functions. The device is created using SONOS technology.

PSoC resembles an ASIC: blocks can be assigned a wide range of functions and interconnected on-chip. Unlike an ASIC, there is no special manufacturing process required to create the custom configuration – only startup code that is created by Cypress' PSoC Designer (for PSoC 1) or PSoC Creator (for PSoC 3 / 4 / 5) IDE.

PSoC resembles an FPGA in that at power up it must be configured, but this configuration occurs by loading instructions from the built-in Flash memory.

PSoC most closely resembles a microcontroller combined with a PLD and programmable analog. Code is executed to interact with the user-specified peripheral functions (called "Components"), using automatically generated APIs and interrupt routines. PSoC Designer or PSoC Creator generate the startup configuration code. Both integrate APIs that initialize the user selected components upon the users needs in a Visual-Studio-like GUI.

Configurable analog and digital blocks

Using configurable analog and digital blocks, designers can create and change mixed-signal embedded applications. The digital blocks are state machines that are configured using the blocks registers. There are two types of digital blocks, Digital Building Blocks (DBBxx) and Digital Communication Blocks (DCBxx). Only the communication blocks can contain serial I/O user modules, such as SPI, UART, etc.

Each digital block is considered an 8-bit resource that designers can configure using pre-built digital functions or user modules (UM), or, by combining blocks, turn them into 16-, 24-, or 32-bit resources. Concatenating UMs together is how 16-bit PWMs and timers are created.

There are two types of analog blocks. The continuous time (CT) blocks are composed of an op-amp circuit and designated as ACBxx where xx is 00–03. The other type is the switch cap (SC) blocks, which allow complex analog signal flows and are designated by ASCxy where x is the row and y is the column of the analog block. Designers can modify and personalize each module to any design.

Programmable routing and interconnect

PSoC mixed-signal arrays' flexible routing allows designers to route signals to and from I/O pins more freely than with many competing microcontrollers. Global buses allow for signal multiplexing and for performing logic operations. Cypress suggests that this allows designers to configure a design and make improvements more easily and faster and with fewer PCB redesigns than a digital logic gate approach or competing microcontrollers with more fixed function pins.

Series

There are five different families of devices, each based around a different microcontroller core:

PSoC 1 – CY8C2xxxx series – M8C core.
PSoC 3 – CY8C3xxxx series – 8051 core.
PSoC 4 – CY8C4xxxx series – ARM Cortex-M0 core.
PSoC 5/5LP – CY8C5xxxx series – ARM Cortex-M3 core.
PSoC 6 – CY8C6xxxx series – ARM Cortex-M4 core with an added ARM Cortex-M0+ core (in some models).

Bluetooth Low Energy

Starting in 2014, Cypress began offering PSoC 4 BLE devices with integrated Bluetooth Low Energy (Bluetooth Smart). This can be used to create connected products leveraging the analog and digital blocks. Users can add and configure the BLE module directly in PSoC creator. Cypress also provides a complete Bluetooth Low Energy stack licensed from Mindtree with both Peripheral and Central functionality. The PSoC 6 series includes versions with BLE including Bluetooth 5 features including extended range or higher speed.

Summary

PSoC 1	PSoC 3	PSoC 4	PSoC 5/5LP	PSoC 6
8-bit M8C core up to 24 MHz, 4 MIPS	8-bit 8051 core (single-cycle) up to 67 MHz, 33 MIPS	32-bit ARM Cortex-M0 up to 48 MHz, ? MIPS	32-bit ARM Cortex-M3 up to 80 MHz, 84 MIPS	32-bit ARM Cortex-M4 (up to 150 MHz) 32-bit ARM Cortex-M0+ (opt. up to 100 MHz)
Flash: 4 KB to 32 KB SRAM: 256 bytes to 2 KB	Flash: 8 KB to 64 KB SRAM: 3 KB to 8 KB	Flash: 16 KB to 256 KB SRAM: 2 KB to 32 KB	Flash: 32 KB to 256 KB SRAM: 8 KB to 64 KB	Flash: 512 KB to 2048 KB SRAM: 128 KB to 512 KB expandable using quad SPI
I²C, SPI, UART, FS USB 2.0	I²C, SPI, UART, LIN, FS USB 2.0, I²S, CAN	I²C, SPI, UART, CAN .	I²C, SPI, UART, LIN, CAN, FS USB 2.0, I²S	I²C, SPI, UART, LIN, BLE (opt.), FS USB 2.0 (opt. host & device)
16 digital PSoC blocks	16 to 24 UDBs (Universal Digital Blocks)	4 to 8 UDBs	20 to 24 UDBs	0 to 12 UDBs
1 Delta-Sigma ADC (6 to 14-bit) 131 ksps @ 8-bit; 1 Sigma-Delta ADC (for capacitive sensing) Up to two DACs (6 to 8-bit)	1 Delta-Sigma ADC (8 to 20-bit) 192 ksps @ 12-bit; Up to four DACs (8-bit)	1 SAR ADC (12-bit) 1 Msps @ 12-bit; Up to two DACs (7 to 8-bit)	1 Delta-Sigma ADC (8 to 20-bit) 192 ksps @12-bit; 2 SAR ADCs (12-bit) 1 Msps @ 12-bit; Up to four DACs (8-bit)	1 SAR ADC (12-bit) 1 MSPS 1 12 Bit Voltage Mode DAC
Up to 64 I/O	Up to 72 I/O	Up to 98 I/O	Up to 72 I/O	Up to 104 I/O
Operation: 1.7 V to 5.25 V Active: 2 mA, Sleep: 3 μA Hibernate: ?	Operation: 0.5 V to 5.5 V Active: 1.2 mA, Sleep: 1 μA, Hibernate: 200 nA	Operation: 1.71 V to 5.5 V Active: 1.6 mA, Sleep: 1.3 μA, Hibernate: 150 nA	Operation: 2.7 V to 5.5 V Active: 2 mA, Sleep: 2 μA, Hibernate: 300 nA
Requires ICE Cube and FlexPods		On-chip SWD, Debug	On-chip JTAG, SWD, SWV, Debug, Trace
CY8CKIT-001 Development Kit	CY8CKIT-001 Development Kit CY8CKIT-030 Development Kit	CY8CKIT-040 4000 Pioneer Kit CY8CKIT-042 4200 Pioneer Kit CY8CKIT-043 4200M Prototyping Kit CY8CKIT-044 4200M Pioneer Kit CY8CKIT-046 4200L Pioneer Kit CY8CKIT-049 4100 Prototype Kit	CY8CKIT-001 Development Kit CY8CKIT-050 Development Kit CY8CKIT-059 Prototype Kit	CY8CKIT-062-BLE Pioneer Kit

Development tools

PSoC Designer

This is the first generation software IDE to design and debug and program the PSoC 1 devices. It introduced unique features including a library of pre-characterized analog and digital peripherals in a drag-and-drop design environment which could then be customized to specific design needs by leveraging the dynamically generated API libraries of code.

PSoC Creator

PSoC Creator is the second generation software IDE to design debug and program the PSoC 3 / 4 / 5 devices. The development IDE is combined with an easy-to-use graphical design editor to form a powerful hardware/software co-design environment. PSoC Creator consists of two basic building blocks. The program allows the user to select, configure and connect existing circuits on the chip and the components which are the equivalent of peripherals on MCUs. What makes PSoC intriguing is the possibility of creating its own application-specific peripherals in hardware. Cypress publishes component packs several times a year. PSoC users get new peripherals for their existing hardware without being charged or having to buy new hardware. PSoC Creator also allows much freedom in the assignment of peripherals to I/O pins.

Cortex-M

Main article: List of ARM Cortex-M development tools

Generic ARM development tools for PSoC 4 and PSoC 5.

Documentation

PSoC 4 / 5

The amount of documentation for all ARM chips is daunting, especially for newcomers. The documentation for microcontrollers from past decades would easily be inclusive in a single document, but as chips have evolved so has the documentation grown. The total documentation is especially hard to grasp for all ARM chips since it consists of documents from the IC manufacturer (Cypress Semiconductor) and documents from CPU core vendor (ARM Holdings).

A typical top-down documentation tree is: manufacturer website, manufacturer marketing slides, manufacturer datasheet for the exact physical chip, manufacturer detailed reference manual that describes common peripherals and aspects of a physical chip family, ARM core generic user guide, ARM core technical reference manual, ARM architecture reference manual that describes the instruction set(s).

PSoC 4 / 5 documentation tree (top to bottom)

PSoC website.
PSoC marketing slides.
PSoC datasheet.
PSoC reference manuals.
ARM core website.
ARM core generic user guide.
ARM core technical reference manual.
ARM architecture reference manual.

Cypress Semiconductor has additional documents, such as: evaluation board user manuals, application notes, getting started guides, software library documents, errata, and more. See External Links section for links to official PSoC and ARM documents.

References

Reuters: "Cypress Hits Half-Billion Mark in Shipments of PSoC Programmable system on a chip Devices" 2009
Circuit Cellar:"PSoC Design Challenge 2002"
"Fully Qualified Production Silicon for Cypress's First Two PSoC® 4 Product Families Is Now Available". yahoo.com. Retrieved April 12, 2018.
Corp., Cypress Semiconductor. "Cypress Offers Complete Portfolio of Flexible PSoC ARM Cortex-M0 and Cortex-M0+ Solutions to Replace Legacy 8-Bit and 16-Bit Platforms". www.prnewswire.com (Press release). Retrieved March 4, 2016.
"Custom Peripherals Surround Cortex-M0 Platform". April 16, 2013.
"PSoC 6 CY8CKIT-062 Pioneer Kit – Cypress – DigiKey". www.digikey.com. Retrieved April 12, 2018.
"PSoC® 4 BLE (Bluetooth Smart)". Retrieved February 12, 2015.
"Cypress offering BLE chipset, Here's what you need to know". Retrieved February 12, 2015.

External links

PSoC Official Documents

PSoC official website
- PSoC Designer software for PSoC 1 family
- PSoC Creator software for PSoC 3 / 4 / 5LP families
- PSoC Programmer software for PSoC 1 / 3 / 4 / 5LP families

ARM Official Documents for PSoC 4 / 5

Main article: ARM Cortex-M external links

Other

PSoC Developer
IoT Expert PSoC Tutorials
Psoc-chile El primer web site en Español sobre Microcontroladore Psoc

v t e System on a chip (SoC)
Components	Microprocessor cores controllers Graphics processing unit (GPU) Image processor Media processor AI accelerator ASIC
Types	Network on a chip (NoC) Multiprocessor SoC (MPSoC) Programmable SoC (PSoC) Microcontroller (MCU)
Alternatives	Multi-chip module (MCM) System in a package (SiP) Package on a package (PoP)
Related	Processor chronology design CPLD Digital signal processor (DSP) Embedded systems FPGA List of SoC suppliers Mobile computing Unified memory

Embedded ARM-based chips

Embedded
microcontrollers

Cortex-M0	Cypress PSoC 4000, 4100, 4100M, 4200, 4200DS, 4200L, 4200M Infineon XMC1000 Nordic nRF51 NXP LPC1100, LPC1200 nuvoTon NuMicro Sonix SN32F700 STMicroelectronics STM32 F0 Toshiba TX00 Vorago VA108x0
Cortex-M0+	Cypress PSoC 4000S, 4100S, 4100S+, 4100PS, 4700S, FM0+ Holtek HT32F52000 Microchip (Atmel) SAM C2, D0, D1, D2, DA, L2, R2, R3 NXP LPC800, LPC11E60, LPC11U60 NXP (Freescale) Kinetis E, EA, L, M, V1, W0 Raspberry Pi RP2040 Renesas Synergy S1 Silicon Labs (Energy Micro) EFM32 Zero, Happy STMicroelectronics STM32 L0
Cortex-M1	Altera FPGAs Cyclone-II, Cyclone-III, Stratix-II, Stratix-III Microsemi (Actel) FPGAs Fusion, IGLOO/e, ProASIC3L, ProASIC3/E Xilinx FPGAs Spartan-3, Virtex-2-3-4
Cortex-M3	Actel SmartFusion, SmartFusion 2 Analog Devices ADuCM300 Cypress PSoC 5000, 5000LP, FM3 Fujitsu FM3 Holtek HT32F Microchip (Atmel) SAM 3A, 3N, 3S, 3U, 3X NXP LPC1300, LPC1700, LPC1800 ON Semiconductor Q32M210 Silicon Labs Precision32 Silicon Labs (Energy Micro) EFM32 Tiny, Gecko, Leopard, Giant STMicroelectronics STM32 F1, F2, L1 Texas Instruments F28, LM3, TMS470, OMAP 4 Toshiba TX03
Cortex-M4	Microchip (Atmel) SAM 4L, 4N, 4S NXP (Freescale) Kinetis K, W2 Renesas RA4W1, RA6M1, RA6M2, RA6M3, RA6T1
Cortex-M4F	Cypress 6200, FM4 Infineon XMC4000 Microchip (Atmel) SAM 4C, 4E, D5, E5, G5 Microchip CEC1302 Nordic nRF52 NXP LPC4000, LPC4300 NXP (Freescale) Kinetis K, V3, V4 Renesas Synergy S3, S5, S7 Silicon Labs (Energy Micro) EFM32 Wonder STMicroelectronics STM32 F3, F4, L4, L4+, WB Texas Instruments LM4F/TM4C, MSP432 Toshiba TX04
Cortex-M7F	Microchip (Atmel) SAM E7, S7, V7 NXP (Freescale) Kinetis KV5x, i.MX RT 10xx, i.MX RT 11xx, S32K3xx STMicroelectronics STM32 F7, H7
Cortex-M23	GigaDevice CD32E2xx Microchip (Atmel) SAM L10, L11, and PIC 32CM-LE 32CM-LS Nuvoton M23xx family, M2xx family, NUC1262, M2L31 Renesas S1JA, RA2A1, RA2L1, RA2E1, RA2E2
Cortex-M33F	Analog Devices ADUCM4 Dialog DA1469x GigaDevice GD32E5, GD32W5 Nordic nRF91, nRF5340, nRF54 NXP LPC5500, i.MX RT600 ON RSL15 Renesas RA4, RA6 ST STM32 H5, L5, U5, WBA Silicon Labs Wireless Gecko Series 2
Cortex-M35P	STMicroelectronics ST33K
Cortex-M55F	Alif Semiconductor Ensemble Infineon PSoC Edge
Cortex-M85F	Renesas RA8

Real-time
microprocessors

Cortex-R4F	Texas Instruments RM4, TMS570 Renesas RZ/T1
Cortex-R5F	Scaleo OLEA Texas Instruments RM57, AM2 Xilinx Versal, ZynqMP, ZynqRF
Cortex-R7F	Renesas RZ/G2E, RZ/G2H, RZ/G2M, RZ/G2N
Cortex-R52F	NXP S32Z, S32E Renesas RZ/N2L, RZ/T2L, RZ/T2M
Cortex-R52+F	STMicroelectronics Stellar G, Stellar P

Microcontrollers

Main

Architectures

Word length

4-bit	Am2900 COP400 MARC4 PPS-4 S1C6x TLCS-47 TMS1000 μCOM-4
8-bit	6800 68HC05 68HC08 68HC11 S08 RS08 6502 65C134 65C265 MELPS 740 78K 8048 8051 XC800 AVR COP8 H8 PIC10/12/16/17/18 ST6/ST7 STM8 Z8 Z80 eZ80 Rabbit 2000 TLCS-870
16-bit	65C816 68HC12/16 80186 C166 CR16/C H8S MSP430 PIC24/dsPIC R8C RL78 TLCS-900 Z8000
32-bit	Am29000 ARC ARM Cortex-M EFM32 LPC SAM STM32 XMC ARM Cortex-R AVR32 CRX FR FR-V H8SX M32R MN103 68000 ColdFire PIC32 PowerPC MPC5xx Propeller SuperH TLCS-900 TriCore V850 RX Xtensa Z80000
64-bit	ARC ARM Cortex-R PowerPC64

Interfaces

Programming	In-circuit serial programming (ICSP) In-system programming (ISP) Program and Debug Interface (PDI) High-voltage serial programming (HVSP) High voltage parallel programming (HVPP) Bootloader ROM aWire
Debugging	Nexus (standard) Joint Test Action Group (JTAG) debugWIRE (Atmel) In-circuit debugging (ICD) In-circuit emulator (ICE) In-target probe (ITP)

Lists