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Standard Cell design involves compiling Hardware definition Language ] designs into stardard logic libraries. The standard libraries consist of a collection of logic functions (and, or, invert, xor, xnor, buffer, etc.) that have both a logical and physical representation. The compiler uses the logical representation to create a netlist. This netlist is read by the appropriate chip ] tools and the physical version of the standard cells are used to translate the netlist into a physical reality. Standard Cell design involves compiling Hardware definition Language ] designs into standard logic libraries. The standard libraries consist of a collection of logic functions (and, or, invert, xor, xnor, buffer, etc.) that have both a logical and physical representation. The compiler uses the logical representation to create a netlist. This netlist is read by the appropriate chip ] tools and the physical version of the standard cells are used to translate the netlist into a physical reality.


Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the silicon chip. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design. Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the silicon chip. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design.

Revision as of 23:10, 24 June 2005

Standard Cell design involves compiling Hardware definition Language HDL designs into standard logic libraries. The standard libraries consist of a collection of logic functions (and, or, invert, xor, xnor, buffer, etc.) that have both a logical and physical representation. The compiler uses the logical representation to create a netlist. This netlist is read by the appropriate chip place and route tools and the physical version of the standard cells are used to translate the netlist into a physical reality.

Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the silicon chip. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design.