| Revision as of 08:43, 12 January 2006 edit69.208.112.160 (talk) Fixed link← Previous edit | Revision as of 11:52, 8 February 2006 edit undoDyl (talk | contribs)Extended confirmed users3,403 edits Category:Electronic design automationNext edit → | ||
| Line 2: | Line 2: | ||
| Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the silicon chip. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design. | Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the silicon chip. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design. | ||
| ] | |||
Revision as of 11:52, 8 February 2006
Standard Cell design involves compiling Hardware Description Language (HDL) designs into standard logic libraries. The standard libraries consist of a collection of logic functions (and, or, invert, xor, xnor, buffer, etc.) that have both a logical and physical representation. The compiler uses the logical representation to create a netlist. This netlist is read by the appropriate chip place and route tools and the physical version of the standard cells are used to translate the netlist into a physical reality.
Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the silicon chip. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design.
Category: