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| Standard Cell design involves compiling ] (HDL) designs into standard logic libraries. The standard libraries consist of a collection of logic functions (and, or, invert, xor, xnor, buffer, etc.) that have both a logical and physical representation. The |
Standard Cell design involves compiling ] (HDL) designs into standard logic libraries. The standard libraries consist of a collection of logic functions (and, or, invert, xor, xnor, buffer, etc.) that have both a logical and physical representation. The logical representation describes the behavior of the cell and can be represented by a truth-table or boolean algebra equation. The physical representation is the implementation of the logical description first as a netlist, which at its lowest level is a nodal description of transistor connections (commonly SPICE). After a transistor level netlist is created, the cell can "layed-out" creating actual physical representations of the transistors and connections in a format that can be manufactured. | ||
| Standard cells are used by synthesis, place and route electronic design automation (EDA) tools. During the synthesis step, the tool decides which logic functions need to actualize the design using the logical representation of the cells. Once the cells are chosen, the place and route tools, having physical information about the cells (size and location of ports) can place the layout representation in an appropriate configuration to route them creating a physical representation of the entire design that can be taken to a fab for manufacturing. | |||
| Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the silicon chip. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design. | Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the silicon chip. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design. | ||
Revision as of 11:25, 16 February 2006
Standard Cell design involves compiling Hardware Description Language (HDL) designs into standard logic libraries. The standard libraries consist of a collection of logic functions (and, or, invert, xor, xnor, buffer, etc.) that have both a logical and physical representation. The logical representation describes the behavior of the cell and can be represented by a truth-table or boolean algebra equation. The physical representation is the implementation of the logical description first as a netlist, which at its lowest level is a nodal description of transistor connections (commonly SPICE). After a transistor level netlist is created, the cell can "layed-out" creating actual physical representations of the transistors and connections in a format that can be manufactured.
Standard cells are used by synthesis, place and route electronic design automation (EDA) tools. During the synthesis step, the tool decides which logic functions need to actualize the design using the logical representation of the cells. Once the cells are chosen, the place and route tools, having physical information about the cells (size and location of ports) can place the layout representation in an appropriate configuration to route them creating a physical representation of the entire design that can be taken to a fab for manufacturing.
Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the silicon chip. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design.
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