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| '''Standard Cell''' design involves compiling ] (HDL) designs into standard logic libraries. The standard cell libraries consist of a collection of logic functions (], ], invert, ], ], buffer, etc.) that have both a logical and physical representation. The logical representation describes the behavior of the cell and can be represented by a truth-table or ] equation. The physical representation is the implementation of the logical description first as a ], which at its lowest level is a nodal description of transistor connections (commonly ]). After a transistor level netlist is created, the cell can be "layed-out" creating actual physical representations of the transistors and connections in a format that can be manufactured. | '''Standard Cell''' design involves compiling ] (HDL) designs into standard logic libraries. The standard cell libraries consist of a collection of logic functions (], ], invert, ], ], buffer, etc.) that have both a logical and physical representation. The logical representation describes the behavior of the cell and can be represented by a truth-table or ] equation. The physical representation is the implementation of the logical description first as a ], which at its lowest level is a nodal description of transistor connections (commonly ]). After a transistor level netlist is created, the cell can be "layed-out" creating actual physical representations of the transistors and connections in a format that can be manufactured. | ||
| Using ] (EDA) tools, standard cells can be synthesized, placed, and routed efficiently and effectively. During the synthesis step, the EDA tool |
Using ] (EDA) tools, standard cells can be synthesized, placed, and routed efficiently and effectively. During the synthesis step, the EDA tool utilizes the logical representation of the cell(s) in order to help determine which logic functions are needed to turn the design reality (i.e., an actual piece of hardware). Once the cells are chosen, the place and route tools, having physical information about the cells (size and location of ports) can place the layout representation in an appropriate configuration to route them. This creates a physical representation of the entire design that can be taken to a lab for manufacturing. | ||
| Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the ]. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design. | Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the ]. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design. | ||
Revision as of 19:47, 30 March 2006
Standard Cell design involves compiling Hardware Description Language (HDL) designs into standard logic libraries. The standard cell libraries consist of a collection of logic functions (AND, OR, invert, XOR, XNOR, buffer, etc.) that have both a logical and physical representation. The logical representation describes the behavior of the cell and can be represented by a truth-table or boolean algebra equation. The physical representation is the implementation of the logical description first as a netlist, which at its lowest level is a nodal description of transistor connections (commonly SPICE). After a transistor level netlist is created, the cell can be "layed-out" creating actual physical representations of the transistors and connections in a format that can be manufactured.
Using Electronic Design Automation (EDA) tools, standard cells can be synthesized, placed, and routed efficiently and effectively. During the synthesis step, the EDA tool utilizes the logical representation of the cell(s) in order to help determine which logic functions are needed to turn the design reality (i.e., an actual piece of hardware). Once the cells are chosen, the place and route tools, having physical information about the cells (size and location of ports) can place the layout representation in an appropriate configuration to route them. This creates a physical representation of the entire design that can be taken to a lab for manufacturing.
Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the integrated circuit. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design.
See also
External links
- Virginia Tech— This is a standard cell library developed by the Virginia Technology VLSI for Telecommunications (VTVT)