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[[Image:Standard Cell2.png|right|thumb|Standard Cell Diagram Design This is a 3-input NAND cell | [[Image:Standard Cell2.png|right|thumb|Standard Cell Diagram Design This is a 3-input NAND cell | ||
© ST Microtechnologies]] | © ST Microtechnologies]] | ||
'''Standard Cell''' is a method of designing an Integrated Circuit (IC). One method of creating a standard cell involves compiling ] (HDL) into standard logic libraries. The standard cell libraries consist of a collection of logic functions (e.g., ], ], ], ], inverters, etc.) that have both a logical and physical representation. The logical representation describes the electronic behavior of the cell and can be represented by a truth-table or ] equation. The physical representation is the implementation of the logical description. Usually, the initial representation is ], which is a nodal description of transistor connections. Programs like ] are powerful tools to facilitate this process. After a transistor-based netlist is created, the cell design is further refined by developing an ideal physical plan of the transistors and connections. This format is the final step before manufacturing an actual piece of hardware. | '''Standard Cell''' is a method of designing an Integrated Circuit (IC). One method of creating a standard cell involves compiling ] (HDL) into standard logic libraries. The standard cell libraries consist of a collection of logic functions (e.g., ], ], ], ], inverters, etc.) that have both a logical and physical representation. The logical representation describes the electronic behavior of the cell and can be represented by a truth-table or ] equation. The physical representation is the implementation of the logical description. Usually, the initial representation is ], which is a nodal description of transistor connections. Programs like ] are powerful tools to facilitate this process. After a transistor-based netlist is created, the cell design is further refined by developing an ideal physical plan of the transistors and connections. This format is the final step before manufacturing an actual piece of hardware. |
Revision as of 20:20, 30 March 2006
Standard Cell is a method of designing an Integrated Circuit (IC). One method of creating a standard cell involves compiling Hardware Description Language (HDL) into standard logic libraries. The standard cell libraries consist of a collection of logic functions (e.g., AND, OR, XOR, XNOR, inverters, etc.) that have both a logical and physical representation. The logical representation describes the electronic behavior of the cell and can be represented by a truth-table or boolean algebra equation. The physical representation is the implementation of the logical description. Usually, the initial representation is netlist, which is a nodal description of transistor connections. Programs like SPICE are powerful tools to facilitate this process. After a transistor-based netlist is created, the cell design is further refined by developing an ideal physical plan of the transistors and connections. This format is the final step before manufacturing an actual piece of hardware.
Electronic Design Automation
Using Electronic Design Automation (EDA) tools, standard cells can be synthesized, placed, and routed efficiently and effectively. During the synthesis step, the EDA tool utilizes the logical representation of the cell(s) in order to help determine which logic functions are needed to turn the design into reality (i.e., an actual piece of hardware). Once the cell's logic functions are chosen, the EDA's placement and routing tools utilize known physical information about the cells (e.g., size and location of ports) to determine how the cell should be layed out, establish the best routing configuration, etc. This process results in physical representation of the entire design. This design can then be taken to a commercial or government laboratory to begin manufacturing and construction.
Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the integrated circuit. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design.
See also
External links
- Virginia Tech— This is a standard cell library developed by the Virginia Technology VLSI for Telecommunications (VTVT)