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| In semiconductor design, '''standard cell''' methodology is a method of designing Application Specific Integrated Circuits (ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low-level VLSI-layout is encapsulated into an abstract logic representation (such as a NAND gate). Cell-based methodology (the general class that standard-cell belongs to) makes it possible for one designer to focus on the high-level (logical function) aspect of digial-design, while another designer focused on the implementation (physical) aspect. Along with ] advances, standard cell methodology was responsible for allowing designers to scale ASICs from comparitively simple single-function ICs (of several thousand gates), to complex multi-million gate devices (SoC). | |||
| '''Standard Cell''' is a method of designing an Integrated Circuit (IC). One method of creating a standard cell involves compiling ] (HDL) into standard logic libraries. The standard cell libraries consist of a collection of logic functions (e.g., ], ], ], ], inverters, etc.) that have both a logical and a physical representation. The logical representation describes the electronic behavior of the cell and can be represented by a truth-table or ] equation. The physical representation is the implementation of the logical description. Usually, the initial design of a future integrated chip is developed as a ], which is a nodal description of transistor connections. ] (CAD) programs like ] are powerful tools to facilitate this process. After a transistor-based netlist is created, the cell design is further refined by developing an ideal physical plan of the transistors and connections. This format is the final step before manufacturing an actual piece of hardware. | |||
| ==Construction of a standard cell== | |||
| ==Electronic Design Automation== | |||
| A standard cell is group of transistor and interconnect structures, which provides a boolean logic function ((e.g., ], ], ], ], inverters) or a storage function (flipflop or latch ). The simplest cells are direct representations of the elemental NAND, NOR, and XOR boolean function, although cells of much greater complexity are commonly used (such as a 2-bit full-adder, or muxed D-input flipflop.) The cell's boolean logic function is called its ''logical view'': functional behavior is captured in the form of a truth-table or ] equation (for combinational logic), or a state-transition table (for seqeuential logic.) | |||
| Using ] (EDA) tools, standard cells can be synthesized, placed, and routed efficiently and effectively. During the synthesis step, the EDA tool utilizes the logical representation of the cell(s) in order to help determine which logic functions are needed to turn the design into reality (i.e., an actual piece of hardware). Once the cell's logic functions are chosen, the EDA's placement and routing tools utilize known physical information about the cells (e.g., size and location of ports) to determine how the cell should be layed out, establish the best routing configuration, etc. This process results in physical representation of the entire design. In logic design, simulation tools, that mimic the behavior of the real physical components but allow the designer to easily peek inside, are an essential part of the designer's arsenal. This design can then be taken to a commercial or government laboratory to begin manufacturing and construction. | |||
| Usually, the initial design of a standard cell is developed at the transistor-level, in the form a transistor ]. The netlist is a nodal description of transistor-devices, their connections to each other, and their terminals (ports) to the external environment. Designers use ] (CAD) programs such as ] to simulate the circuit-behavior of the netlist, by declaring input stimulus (voltage or current waveforms) and then calculating the circuit's time-domain (analog) response. The simulations also verify the netlist's logical (digital) behavior, mentioned beforehand, and predict other pertinent parameters (power-consumption, signal propogation delay. | |||
| ⚫ | Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the ]. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design. | ||
| Since the logical and netlist views are only useful to abstract (algebraic) simulation, and not device fabrication, a standard cell must possess a physical representation. From a manufacturing perspective, the standard cell's VLSI layout is the most important view. In layman's terms, the layout is an abstract drawing of polygons. The layout is organized into base-layers, which correspond to the different structures of the transistor devices, and interconnect-lines, which join together the terminals of the transistor formations. In common design practice, the layout-view is the lowest level of design abstraction -- it is closest to an actual "manufacturing blueprint" of the standard-cell. | |||
| For a typical boolean function, many different transistor netlists exist that are functionally equivalent. Likewise, for a typical netlist, there exist many different layouts that fit the netlist's performance parameters. The designer's challenge is to minimize the manufacturing cost of the standard-cell's layout (generally by minimizing the circuit's die-area), while still meeting the cell's speed and power performance requirements. Consequently, IC-layout is a highly labour intensive job, despite the existence of design tools to aide this process. | |||
| ==Application of standard cell== | |||
| Strictly speaking, a 2-input NAND or NOR function is sufficient to form any abritrary boolean function set. But in modern ASIC design, standard cell methodology is practiced with a sizeable library (or libraries) of cells. The library usually contains multiple implmentations of the same logic-function, differing by area and speed. This variety enhances the efficiency of automated synthesis, place and route (SPR) tools. Indirectly, it also gives the designer greater freedom to perform implementation tradeoffs (area vs speed vs power consumption.) A complete group of standard-cell descriptions is commonly called a technology-library. | |||
| Commercially available ] (EDA) tools use the technology-libraries to automate synthesis, placement, and routing of a digital ASIC. The technology library is developed and distributed by the ] operator. The library (along with a design netlist format) is the basis for exchanging design information between different phases of the SPR process. | |||
| ===Synthesis=== | |||
| Using the technology-library's cell logical-view, the synthesis-tool performs the process of mathematically transforming the ASIC's register-transfer level (RTL) description into technology-dependent gate-netlist. (This process is analogous to a software compiler converting a high-level C-program listing into a processor-dependent, assembly language listing.) | |||
| The gate-netlist is the standard-cell representation of the ASIC design, at the logical-view level. It consists of instances of the standard-cell library gates, and port-connectivity between gates. Proper synthesis techniques ensure mathematical equivalency between the synthesized gate-netlist and original RTL-description. The netlist contains no unmapped (RTL) statements and declarations. | |||
| ===Placement=== | |||
| The placer tool starts the physical implementation of the ASIC. With a 2-D floorplan provided by the ASIC-designer, the placer tool assigns locations for each gate in the gate-netlist. The resulting placed-gates contains physical-location of each of the netlist's standard-cells, but retains the abstract nodal-description of the gates' port-connectivity (i.e. how the gates' terminals are wired to each other.) | |||
| ⚫ | Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the ]. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design. Placers obey certain rules: Each gate is assigned a unique (exclusive) location on the diemap. A given gate is placed once, and may not occupy or overlap the location of any other gate. | ||
| ===Routing=== | |||
| Using the placed-gates netlist and the layout-view of the library, the router adds both signal-connect lines and power-supply lines to the placed-gates diemap. The fully-routed (physical) netlist contains the listing of gates (from synthesis), the placement of each gate (from placement), and the drawn interconnects (from routing.) | |||
| ===DRC/LVS=== | |||
| Design Rule Check (DRC) and Layout Vs Schematic (LVS) are verification processes. Reliable device fabrication at modern deep submicron (0.13u and below) requires strict observance of transistor spacing, metal-layer thickness, and power-density rules. DRC exhaustively compares the fully-routed netlist against a stack of "foundry design rules" (from the foundry operator), then flags any observed violations. | |||
| // LVS - TODO (I'm not a backend person.) | |||
| ==Other cell-based methodologies== | |||
| Standard-cell falls into a more general class of design-automation called cell based design. Gate-array/structured ASICs, FPGAs, and CPLDs are variations on cell-based design. From the designer's standpoint, all share the same input frontend: an RTL description of the design. But all 3 differ substantially in the details of the SPR flow and physical implementation. | |||
| ] | ] | ||
Revision as of 01:20, 9 April 2006
In semiconductor design, standard cell methodology is a method of designing Application Specific Integrated Circuits (ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low-level VLSI-layout is encapsulated into an abstract logic representation (such as a NAND gate). Cell-based methodology (the general class that standard-cell belongs to) makes it possible for one designer to focus on the high-level (logical function) aspect of digial-design, while another designer focused on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard cell methodology was responsible for allowing designers to scale ASICs from comparitively simple single-function ICs (of several thousand gates), to complex multi-million gate devices (SoC).
Construction of a standard cell
A standard cell is group of transistor and interconnect structures, which provides a boolean logic function ((e.g., AND, OR, XOR, XNOR, inverters) or a storage function (flipflop or latch ). The simplest cells are direct representations of the elemental NAND, NOR, and XOR boolean function, although cells of much greater complexity are commonly used (such as a 2-bit full-adder, or muxed D-input flipflop.) The cell's boolean logic function is called its logical view: functional behavior is captured in the form of a truth-table or boolean algebra equation (for combinational logic), or a state-transition table (for seqeuential logic.)
Usually, the initial design of a standard cell is developed at the transistor-level, in the form a transistor netlist. The netlist is a nodal description of transistor-devices, their connections to each other, and their terminals (ports) to the external environment. Designers use Computer Aided Design (CAD) programs such as SPICE to simulate the circuit-behavior of the netlist, by declaring input stimulus (voltage or current waveforms) and then calculating the circuit's time-domain (analog) response. The simulations also verify the netlist's logical (digital) behavior, mentioned beforehand, and predict other pertinent parameters (power-consumption, signal propogation delay.
Since the logical and netlist views are only useful to abstract (algebraic) simulation, and not device fabrication, a standard cell must possess a physical representation. From a manufacturing perspective, the standard cell's VLSI layout is the most important view. In layman's terms, the layout is an abstract drawing of polygons. The layout is organized into base-layers, which correspond to the different structures of the transistor devices, and interconnect-lines, which join together the terminals of the transistor formations. In common design practice, the layout-view is the lowest level of design abstraction -- it is closest to an actual "manufacturing blueprint" of the standard-cell.
For a typical boolean function, many different transistor netlists exist that are functionally equivalent. Likewise, for a typical netlist, there exist many different layouts that fit the netlist's performance parameters. The designer's challenge is to minimize the manufacturing cost of the standard-cell's layout (generally by minimizing the circuit's die-area), while still meeting the cell's speed and power performance requirements. Consequently, IC-layout is a highly labour intensive job, despite the existence of design tools to aide this process.
Application of standard cell
Strictly speaking, a 2-input NAND or NOR function is sufficient to form any abritrary boolean function set. But in modern ASIC design, standard cell methodology is practiced with a sizeable library (or libraries) of cells. The library usually contains multiple implmentations of the same logic-function, differing by area and speed. This variety enhances the efficiency of automated synthesis, place and route (SPR) tools. Indirectly, it also gives the designer greater freedom to perform implementation tradeoffs (area vs speed vs power consumption.) A complete group of standard-cell descriptions is commonly called a technology-library.
Commercially available Electronic Design Automation (EDA) tools use the technology-libraries to automate synthesis, placement, and routing of a digital ASIC. The technology library is developed and distributed by the foundry operator. The library (along with a design netlist format) is the basis for exchanging design information between different phases of the SPR process.
Synthesis
Using the technology-library's cell logical-view, the synthesis-tool performs the process of mathematically transforming the ASIC's register-transfer level (RTL) description into technology-dependent gate-netlist. (This process is analogous to a software compiler converting a high-level C-program listing into a processor-dependent, assembly language listing.)
The gate-netlist is the standard-cell representation of the ASIC design, at the logical-view level. It consists of instances of the standard-cell library gates, and port-connectivity between gates. Proper synthesis techniques ensure mathematical equivalency between the synthesized gate-netlist and original RTL-description. The netlist contains no unmapped (RTL) statements and declarations.
Placement
The placer tool starts the physical implementation of the ASIC. With a 2-D floorplan provided by the ASIC-designer, the placer tool assigns locations for each gate in the gate-netlist. The resulting placed-gates contains physical-location of each of the netlist's standard-cells, but retains the abstract nodal-description of the gates' port-connectivity (i.e. how the gates' terminals are wired to each other.)
Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the integrated circuit. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design. Placers obey certain rules: Each gate is assigned a unique (exclusive) location on the diemap. A given gate is placed once, and may not occupy or overlap the location of any other gate.
Routing
Using the placed-gates netlist and the layout-view of the library, the router adds both signal-connect lines and power-supply lines to the placed-gates diemap. The fully-routed (physical) netlist contains the listing of gates (from synthesis), the placement of each gate (from placement), and the drawn interconnects (from routing.)
DRC/LVS
Design Rule Check (DRC) and Layout Vs Schematic (LVS) are verification processes. Reliable device fabrication at modern deep submicron (0.13u and below) requires strict observance of transistor spacing, metal-layer thickness, and power-density rules. DRC exhaustively compares the fully-routed netlist against a stack of "foundry design rules" (from the foundry operator), then flags any observed violations. // LVS - TODO (I'm not a backend person.)
Other cell-based methodologies
Standard-cell falls into a more general class of design-automation called cell based design. Gate-array/structured ASICs, FPGAs, and CPLDs are variations on cell-based design. From the designer's standpoint, all share the same input frontend: an RTL description of the design. But all 3 differ substantially in the details of the SPR flow and physical implementation.
See also
External links
- VLSI Technology— This site contains support material for a book that Graham Petley is writing, The Art of Standard Cell Library Design
- Virginia Tech— This is a standard cell library developed by the Virginia Technology VLSI for Telecommunications (VTVT)