Intel 8086: Difference between revisions

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	{{Infobox CPU
	\| name = Intel 8086
	\| image = KL_Intel_D8086.jpg
	\| caption =
	\| produced-start = 1978
	\| produced-end = 1990s
	\| slowest = 5 \| slow-unit = MHz
	\| fastest = 10 \| fast-unit = MHz
	\| manuf1 = ], ], ], ], ] (]), ], ], ], ], ] (Matsushita).
	\| arch = ]
	\| pack1 = 40 pin ]
	\| predecessor = (])<!-- not instruction set compatible -->
	\| variant = ]
	\| successor = ] and ] (both of which were introduced in early 1982)
	\| size-from = 3 ]
	\| transistors-from = 29,000
	}}

	The '''8086'''<ref>{{cite web
	\|title=Microprocessor Hall of Fame
	\|url=http://www.intel.com/museum/online/hist%5Fmicro/hof/
	\|publisher=Intel
	\|accessdate=2007-08-11
	\|archiveurl=http://web.archive.org/web/20070706032836/http://www.intel.com/museum/online/hist_micro/hof/\|archivedate=2007-07-06
	}}</ref> ("''eighty eighty-six''", also called '''iAPX 86''')<ref name="i286"> (page 1-1)</ref> is a ] ] chip designed by ] between early 1976 and mid-1978, when it was released. The ], released in 1979, was a slightly modified chip with an external 8-bit ] (allowing the use of cheaper and fewer supporting ]s<ref group="note" >Fewer TTL buffers, latches, multiplexers (although the amount of TTL <u>logic</u> was not drastically reduced). It also permitted the use of cheap 8080-family ICs, where the 8254 CTC, ] PIO, and 8259 PIC were used in the IBM PC design. In addition, it made PCB layout simpler and boards cheaper, as well as demanding fewer (1- or 4-bit wide) DRAM chips.</ref>), and is notable as the processor used in the original ] design, including the widespread version called ].

	The 8086 gave rise to the ] which eventually became Intel's most successful line of processors.

	==History==

	===Background===
	In 1972, Intel launched the ], the first 8-bit microprocessor.<ref group="note" >using enhancement load ] (requiring 14 ], achieving TTL compatibility by having V<sub>CC</sub> at +5 V and V<sub>DD</sub> at –9 V)</ref> It implemented an ] designed by ] corporation with programmable ] in mind, which also proved to be fairly general purpose. The device needed several additional ]s to produce a functional computer, in part due to it being packaged in a small 18-pin "memory package", which ruled out the use of a separate address bus (Intel was primarily a ] manufacturer at the time).

	Two years later, Intel launched the ],<ref group="note" >using non-saturated enhancement load ] (demanding a higher gate voltage for the load transistor gates)</ref> employing the new 40-pin ]s originally developed for ] ICs to enable a separate address bus. It had an extended instruction set that was ] (not ]) compatible with the 8008 and also included some ] instructions to make programming easier. The 8080 device, often described as "the first truly useful microprocessor"{{citation needed\|date=December 2014}}, was eventually replaced by the ] based ] (1977) which sufficed with a single +5 V power supply instead of the three different operating voltages of earlier chips.<ref group="note" >made possible with depletion load nMOS logic (the 8085 was later made using HMOS processing, just like the 8086)</ref> Other well known 8-bit microprocessors that emerged during these years were ] (1974), ] (1975), ] (1975), ] (1976), and ] (1978).

	===The first x86 design===
	]
	The 8086 project started in May 1976 and was originally intended as a temporary substitute for the ambitious and delayed ] project. It was an attempt to draw attention from the less-delayed 16- and 32-bit processors of other manufacturers (such as ], ], and ]) and at the same time to counter the threat from the ] (designed by former Intel employees), which became very successful. Both the architecture and the physical chip were therefore developed rather quickly by a small group of people, and using the same basic ] elements and physical implementation techniques as employed for the slightly older ] (and for which the 8086 also would function as a continuation).

	Marketed as ], the 8086 was designed to allow ] for the 8008, 8080, or 8085 to be automatically converted into equivalent (suboptimal) 8086 source code, with little or no hand-editing. The programming model and instruction set was (loosely) based on the 8080 in order to make this possible. However, the 8086 design was expanded to support full 16-bit processing, instead of the fairly basic 16-bit capabilities of the 8080/8085.

	New kinds of instructions were added as well; full support for signed integers, base+offset addressing, and self-repeating operations were akin to the ] design<ref>, PC World, June 17, 2008</ref> but were all made slightly more general in the 8086. Instructions directly supporting ] ]-family languages such as ] and ] were also added. According to principal architect ], this was a result of a more software centric approach than in the design of earlier Intel processors (the designers had experience working with compiler implementations). Other enhancements included ]d multiply and divide instructions and a bus structure better adapted to future coprocessors (such as ] and ]) and multiprocessor systems.

	The first revision of the instruction set and high level architecture was ready after about three months,<ref group="note" >Rev.0 of the instruction set and architecture was ready in about three months, according to Morse.</ref> and as almost no CAD tools were used, four engineers and 12 layout people were simultaneously working on the chip.<ref group="note" >Using ], light boards, rulers, electric erasers, and a ] (according to Jenny Hernandez, member of the 8086 design team, in a statement made on Intel's webpage for its 25th birthday).</ref> The 8086 took a little more than two years from idea to working product, which was considered rather fast for a complex design in 1976–1978.

	The 8086 was sequenced<ref group="note" >8086 used less microcode than many competitors' designs, such as the MC68000 and others</ref> using a mixture of ]<ref>Randall L. Geiger, Phillip E. Allen, Noel R. Strader ''VLSI design techniques for analog and digital circuits'', McGraw-Hill Book Co., 1990, ISBN 0-07-023253-9, page 779 "Random Logic vs. Structured Logic Forms", illustration of use of "random" describing CPU control logic</ref> and ] and was implemented using depletion-load nMOS circuitry with approximately 20,000 active ]s (29,000 counting all ] and ] sites). It was soon moved to a new refined nMOS manufacturing process called ] (for High performance MOS) that Intel originally developed for manufacturing of fast ] products.<ref group="note" >Fast static RAMs in MOS technology (as fast as bipolar RAMs) was an important product for Intel during this period.</ref> This was followed by HMOS-II, HMOS-III versions, and, eventually, a fully static ] version for battery powered devices, manufactured using Intel's ] processes.<ref group="note" >CHMOS is Intel's name for CMOS circuits manufactured using processing steps very similar to ].</ref> The original chip measured 33 mm² and minimum feature size was 3.2 μm.

	The architecture was defined by ] with some help and assistance by Bruce Ravenel (the architect of the 8087) in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development team<ref group="note" >Other members of the design team were Peter A.Stoll and Jenny Hernandez.</ref> and Bill Pohlman the manager for the project. The legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers; the 8086 also lent its last two digits to later extended versions of the design, such as the ] and the ], all of which eventually became known as the ] family. (Another reference is that the ] for Intel devices is 8086<sub>h</sub>.)

	==Details==
	]
	{\| class="infobox" style="font-size:88%;"
	\|-
	\|align="center" \|''Intel 8086 registers''
	\|-
	\|
	{\| style="font-size:88%;"
	\|-
	\| style="width:10px; text-align:center;"\| <sup>1</sup><sub>9</sub>
	\| style="width:10px; text-align:center;"\| <sup>1</sup><sub>8</sub>
	\| style="width:10px; text-align:center;"\| <sup>1</sup><sub>7</sub>
	\| style="width:10px; text-align:center;"\| <sup>1</sup><sub>6</sub>
	\| style="width:10px; text-align:center;"\| <sup>1</sup><sub>5</sub>
	\| style="width:10px; text-align:center;"\| <sup>1</sup><sub>4</sub>
	\| style="width:10px; text-align:center;"\| <sup>1</sup><sub>3</sub>
	\| style="width:10px; text-align:center;"\| <sup>1</sup><sub>2</sub>
	\| style="width:10px; text-align:center;"\| <sup>1</sup><sub>1</sub>
	\| style="width:10px; text-align:center;"\| <sup>1</sup><sub>0</sub>
	\| style="width:10px; text-align:center;"\| <sup>0</sup><sub>9</sub>
	\| style="width:10px; text-align:center;"\| <sup>0</sup><sub>8</sub>
	\| style="width:10px; text-align:center;"\| <sup>0</sup><sub>7</sub>
	\| style="width:10px; text-align:center;"\| <sup>0</sup><sub>6</sub>
	\| style="width:10px; text-align:center;"\| <sup>0</sup><sub>5</sub>
	\| style="width:10px; text-align:center;"\| <sup>0</sup><sub>4</sub>
	\| style="width:10px; text-align:center;"\| <sup>0</sup><sub>3</sub>
	\| style="width:10px; text-align:center;"\| <sup>0</sup><sub>2</sub>
	\| style="width:10px; text-align:center;"\| <sup>0</sup><sub>1</sub>
	\| style="width:10px; text-align:center;"\| <sup>0</sup><sub>0</sub>
	\| style="width:auto; background:white; color:black" \| ''(bit position)''
	\|-
	\|colspan="21" \| '''Main registers''' <br>
	\|- style="background:silver;color:black"
	\| style="text-align:center; background:white" colspan="4"\|
	\| style="text-align:center;" colspan="8"\| AH
	\| style="text-align:center;" colspan="8"\| AL
	\| style="background:white; color:black;"\| ''']''' (primary accumulator)
	\|- style="background:silver;color:black"
	\| style="text-align:center; background:white" colspan="4"\|
	\| style="text-align:center;" colspan="8"\| BH
	\| style="text-align:center;" colspan="8"\| BL
	\| style="background:white; color:black;"\| '''BX''' (base, accumulator)
	\|- style="background:silver;color:black"
	\| style="text-align:center; background:white" colspan="4"\|
	\| style="text-align:center;" colspan="8"\| CH
	\| style="text-align:center;" colspan="8"\| CL
	\| style="background:white; color:black;"\| '''CX''' (counter, accumulator)
	\|- style="background:silver;color:black"
	\| style="text-align:center; background:white" colspan="4"\|
	\| style="text-align:center;" colspan="8"\| DH
	\| style="text-align:center;" colspan="8"\| DL
	\| style="background:white; color:black;"\| '''DX''' (accumulator, other functions)
	\|-
	\|colspan="21" \| '''Index registers''' <br>
	\|- style="background:silver;color:black"
	\| style="text-align:center;background:#DDD" colspan="4"\| 0 0 0 0
	\| style="text-align:center;" colspan="16"\| ]
	\| style="background:white; color:black;"\| '''S'''ource '''I'''ndex
	\|- style="background:silver;color:black"
	\| style="text-align:center;background:#DDD" colspan="4"\| 0 0 0 0
	\| style="text-align:center;" colspan="16"\| DI
	\| style="background:white; color:black;"\| '''D'''estination '''I'''ndex
	\|- style="background:silver;color:black"
	\| style="text-align:center;background:#DDD" colspan="4"\| 0 0 0 0
	\| style="text-align:center;" colspan="16"\| BP
	\| style="background:white; color:black;"\| '''B'''ase '''P'''ointer
	\|- style="background:silver;color:black"
	\| style="text-align:center;background:#DDD" colspan="4"\| 0 0 0 0
	\| style="text-align:center;" colspan="16"\| ]
	\| style="background:white; color:black;"\| '''S'''tack '''P'''ointer
	\|-
	\|colspan="21" \| '''Program counter''' <br>
	\|- style="background:silver;color:black"
	\| style="text-align:center;background:#DDD" colspan="4"\| 0 0 0 0
	\| style="text-align:center;" colspan="16"\| ]
	\| style="background:white; color:black;"\| '''I'''nstruction '''P'''ointer
	\|-
	\|colspan="21" \| '''Segment registers''' <br>
	\|- style="background:silver;color:black"
	\| style="text-align:center;" colspan="16"\| CS
	\| style="text-align:center;background:#DDD" colspan="4"\| 0 0 0 0
	\| style="background:white; color:black;"\| '''C'''ode '''S'''egment
	\|- style="background:silver;color:black"
	\| style="text-align:center;" colspan="16"\| DS
	\| style="text-align:center;background:#DDD" colspan="4"\| 0 0 0 0
	\| style="background:white; color:black;"\| '''D'''ata '''S'''egment
	\|- style="background:silver;color:black"
	\| style="text-align:center;" colspan="16"\| ES
	\| style="text-align:center;background:#DDD" colspan="4"\| 0 0 0 0
	\| style="background:white; color:black;"\| '''E'''xtra'''S'''egment
	\|- style="background:silver;color:black"
	\| style="text-align:center;" colspan="16"\| SS
	\| style="text-align:center;background:#DDD" colspan="4"\| 0 0 0 0
	\| style="background:white; color:black;"\| '''S'''tack '''S'''egment
	\|-
	\|colspan="21" \| '''Status register'''
	\|- style="background:silver;color:black"
	\| style="text-align:center; background:white" colspan="4"\|
	\| style="text-align:center;"\| -
	\| style="text-align:center;"\| -
	\| style="text-align:center;"\| -
	\| style="text-align:center;"\| -
	\| style="text-align:center;"\| ]
	\| style="text-align:center;"\| ]
	\| style="text-align:center;"\| ]
	\| style="text-align:center;"\| ]
	\| style="text-align:center;"\| ]
	\| style="text-align:center;"\| ]
	\| style="text-align:center;"\| -
	\| style="text-align:center;"\| ]
	\| style="text-align:center;"\| -
	\| style="text-align:center;"\| ]
	\| style="text-align:center;"\| -
	\| style="text-align:center;"\| ]
	\| style="background:white; color:black" \| Flags
	\|}
	\|}

	===Buses and operation===
	All internal registers, as well as internal and external data buses, are 16 bits wide, which firmly established the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus provides a 1 ] physical address space (2<sup>20</sup> = 1,048,576). This address space is addressed by means of internal memory "segmentation". The data bus is ] with the address bus in order to fit all of the control lines into a standard 40-pin ]. It provides a 16-bit I/O address bus, supporting 64 ] of separate I/O space. The maximum linear address space is limited to 64 KB, simply because internal address/index registers are only 16 bits wide. Programming over 64 KB memory boundaries involves adjusting the segment registers (see below); this difficulty existed until the ] architecture introduced wider (32-bit) registers (the memory management hardware in the ] did not help in this regard, as its registers are still only 16 bits wide).

	Some of the control pins, which carry essential signals for all external operations, have more than one function depending upon whether the device is operated in ''min'' or ''max'' mode. The former mode was intended for small single-processor systems, while the latter was for medium or large systems using more than one processor.

	===Registers and instructions===
	The 8086 has eight more or less general 16-bit ] (including the ] but excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as twice as many 8-bit registers (see figure) while the other four, BP, SI, DI, SP, are 16-bit only.

	Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the ''destination'', while the other operand, the ''source'', can be either ''register'' or ''immediate''. A single memory location can also often be used as both ''source'' and ''destination'' which, among other factors, further contributed to a ] comparable to (and often better than) most eight-bit machines at the time.

	The degree of generality of most registers are much greater than in the 8080 or 8085. However, 8086 registers were more specialized than in most contemporary ]s and are also used implicitly by some instructions. While perfectly sensible for the assembly programmer, this made register allocation for compilers more complicated compared to more orthogonal 16-bit and 32-bit processors of the time such as the ], ], ], ] etc. On the other hand, being more regular than the rather minimalistic but ubiquitous 8-bit microprocessors such as the ], ], ], ], ], ], and other contemporary accumulator based machines, it was significantly easier to construct an efficient ] for the 8086 architecture.

	Another factor for this was that the 8086 also introduced some new instructions (not present in the 8080 and 8085) to better support stack-based high-level programming languages such as Pascal and ]; some of the more useful instructions were '''push''' ''mem-op'', and '''ret''' ''size'', supporting the "Pascal ]" directly. (Several others, such as '''push''' ''immed'' and '''enter''', were added in the subsequent 80186, 80286, and 80386 processors.)

	A 64 KB (one segment) ] growing towards lower addresses is supported in ]; 16-bit words are pushed onto the stack, and the top of the stack is pointed to by SS:SP. There are 256 ]s, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the ]es.

	The 8086 has 64 K of 8-bit (or alternatively 32 K of 16-bit word) ] space.

	===Flags===
	8086 has a 16-bit ]. Nine of these condition code flags are active, and indicate the current state of the processor: ] (CF), ] (PF), ] (AF), ] (ZF), ] (SF), ] (TF), ] (IF), ] (DF), and ] (OF).

	===Segmentation===
	{{see also\|x86 memory segmentation}}

	There are also four 16-bit ] registers (see figure) that allow the 8086 ] to access one ] of memory in an unusual way. Rather than concatenating the segment register with the address register, as in most processors whose address space exceeded their register size, the 8086 shifts the 16-bit segment only four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, each external address can be referred to by 2<sup>12</sup> = 4096 different segment:offset pairs.

	{\| style="margin-left:5em"
	\|-
	\| <tt>  </tt><tt style="background:#DED">0110 1000 1000 0111</tt><tt> 0000</tt>
	\| '''Segment''',
	\| 16 bits, shifted 4 bits left
	\|-
	\| <tt>+      </tt><tt style="background:#DDF">0011 0100 1010 1001</tt>
	\| '''Offset''',
	\| 16 bits
	\|- style="text-decoration:line-through"
	\| <tt>                          </tt>
	\|
	\|-
	\| <tt>  </tt><tt style="background:#FDF">0110 1011 1101 0001 1001</tt>
	\| '''Address''',
	\| 20 bits
	\|}

	Although considered complicated and cumbersome by many programmers, this scheme also has advantages; a small program (less than 64 KB) can be loaded starting at a fixed offset (such as 0000) in its own segment, avoiding the need for ], with at most 15 bytes of alignment waste.

	Compilers for the 8086 family commonly support two types of ], ''near'' and ''far''. Near pointers are 16-bit offsets implicitly associated with the program's code or data segment and so can be used only within parts of a program small enough to fit in one segment. Far pointers are 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also support ''huge'' pointers, which are like far pointers except that ] on a huge pointer treats it as a linear 20-bit pointer, while pointer arithmetic on a far pointer ] within its 16-bit offset without touching the segment part of the address.

	To avoid the need to specify ''near'' and ''far'' on numerous pointers, data structures, and functions, compilers also support "memory models" which specify default pointer sizes. The ''tiny'' (max 64K), ''small'' (max 128K), ''compact'' (data > 64K), ''medium'' (code > 64K), ''large'' (code,data > 64K), and ''huge'' (individual arrays > 64K) models cover practical combinations of near, far, and huge pointers for code and data. The ''tiny'' model means that code and data are shared in a single segment, just as in most 8-bit based processors, and can be used to build '']'' files for instance. Precompiled libraries often came in several versions compiled for different memory models.

	According to Morse et al., the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16 MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1 MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low cost 40-pin package for the additional four address bus pins.<ref>Intel 8008 to 8086 by Stephen P. Morse et al.</ref>

	In principle, the address space of the x86 series ''could'' have been extended in later processors by increasing the shift value, as long as applications obtained their segments from the operating system and did not make assumptions about the equivalence of different segment:offset pairs.<ref group="note" >Some 80186 clones did change the shift value, but were never commonly used in desktop computers.</ref> In practice the use of "huge" pointers and similar mechanisms was widespread and the flat 32-bit addressing made possible with the 32-bit offset registers in the 80386 eventually extended the limited addressing range in a more general way (see below).

	Intel could have decided to implement memory in 16 bit words (which would have eliminated the {{overline\|BHE}} signal along with much of the address bus complexities already described). This would mean that all instruction object codes and data would have to be accessed in 16-bit units. Users of the ] long ago realized, in hindsight, that the processor makes very efficient use of its memory. By having a large number of 8-bit object codes, the 8080 produces object code as compact as some of the most powerful minicomputers on the market at the time.<ref name="Osborne">Osborne 16 bit Processor Handbook (Adam Osborne & Gerry Kane) ISBN 0-931988-43-8</ref>{{rp\|5–26}}

	If the 8086 is to retain 8-bit object codes and hence the efficient memory use of the 8080, then it cannot guarantee that (16-bit) opcodes and data will lie on an even-odd byte address boundary. The first 8-bit opcode will shift the next 8-bit instruction to an odd byte or a 16-bit instruction to an odd-even byte boundary. By implementing the {{overline\|BHE}} signal and the extra logic needed, the 8086 has allowed instructions to exist as 1-byte, 3-byte or any other odd byte object codes.<ref name="Osborne"/>{{rp\|5–26}}

	Simply put: this is a trade off. If memory addressing is simplified so that memory is only accessed in 16-bit units, memory will be used less efficiently. Intel decided to make the logic more complicated, but memory use more efficient. This was at a time when memory size was considerably smaller, and at a premium, than that which users are used to today.<ref name="Osborne"/>{{rp\|5–26}}

	====Porting older software====
	Small programs could ignore the segmentation and just use plain 16-bit addressing. This allowed ] software to be quite easily ported to the 8086. The authors of MS-DOS took advantage of this by providing an ] very similar to ] as well as including the simple ''.com'' executable file format, identical to CP/M. This was important when the 8086 and MS-DOS were new, because it allowed many existing CP/M (and other) applications to be quickly made available, greatly easing acceptance of the new platform.

	===Example code===
	The following 8086/8088 ] source code is for a subroutine named <code>_memcpy</code> that copies a block of data bytes of a given size from one location to another. The data block is copied one byte at a time, and the data movement and looping logic utilizes 16-bit operations.

	<!--NOTE: This is not intended to be optimized code, but to illustrate the variety of instructions available on the CPU-->
	<!--NOTE: The hex codes were assembled by hand, so there may be errors-->
	{\|
	\|
	<pre>











	0000:1000

	0000:1000
	0000:1000 55
	0000:1001 89 E5
	0000:1003 06
	0000:1004 8B 4E 06
	0000:1007 E3 11
	0000:1009 8B 76 04
	0000:100C 8B 7E 02
	0000:100F 1E
	0000:1010 07

	0000:1011 8A 04
	0000:1013 88 05
	0000:1015 46
	0000:1016 47
	0000:1017 49
	0000:1018 75 F7

	0000:101A 07
	0000:101B 5D
	0000:101C 29 C0
	0000:101E C3
	0000:101F
	</pre>
	\|
	<source lang="nasm">
	; _memcpy(dst, src, len)
	; Copy a block of memory from one location to another.
	;
	; Entry stack parameters
	; = len, Number of bytes to copy
	; = src, Address of source data block
	; = dst, Address of target data block
	;
	; Return registers
	; AX = Zero

	org 1000h ; Start at 0000:1000h

	_memcpy proc
	push bp ; Set up the call frame
	mov bp,sp
	push es ; Save ES
	mov cx, ; Set CX = len
	jcxz done ; If len=0, return
	mov si, ; Set SI = src
	mov di, ; Set DI = dst
	push ds ; Set ES = DS
	pop es

	loop mov al, ; Load AL from
	mov ,al ; Store AL to
	inc si ; Increment src
	inc di ; Increment dst
	dec cx ; Decrement len
	jnz loop ; Repeat the loop

	done pop es ; Restore ES
	pop bp ; Restore previous call frame
	sub ax,ax ; Set AX = 0
	ret ; Return
	end proc
	</source>
	\|}

	The code above uses the BP (base pointer) register to establish a ], an area on the stack that contains all of the parameters and local variables for the execution of the subroutine. This kind of ] supports ] and ] code, and has been used by most ALGOL-like languages since the late 1950s. The ES segment register is saved on the stack and replaced with the value of the DS segment register, so that the {{code\|MOV}} {{code\|AL}} instructions will operate within the same source and destination data segment. Before returning, the subroutine restores the previous value of the ES register.

	The above routine is a rather cumbersome way to copy blocks of data. Provided the source and the destination blocks reside within single 65,536 byte segments (a requirement of the above routine), advantage can be taken of the 8086's block <code>MOV</code> instructions. The loop section of the above can be replaced by:
	{\|
	\|
	<pre>
	0000:1011 F2
	0000:1012 A5
	</pre>
	\|
	<source lang=nasm>
	loop rep ; Repeat until CX=0
	movsw ; Move the data block
	</source>
	\|}
	This copies the block of data one word at a time. The <code>REP</code> instruction causes the following <code>MOVSW</code> to repeat until CX=0, automatically incrementing SI and DI as it repeats. Alternatively the <code>MOVSB</code> or <code>MOVSD</code> instructions can be used to copy single bytes or double words at a time. Most assemblers will assemble correctly if the <code>REP</code> instruction is used as a prefix to <code>MOVSW</code> as in <code>REP MOVSW</code>.

	This routine will operate correctly if interrupted, because the program counter will continue to point to the <code>REP</code> instruction until the block copy is completed. The copy will therefore continue from where it left off when the interrupt service routine returns control.

	===Performance===
	]

	Although partly shadowed by other design choices in this particular chip, the ] address and ] limited performance slightly; transfers of 16-bit or 8-bit quantities were done in a four-clock memory access cycle, which was faster on 16-bit, although slower on 8-bit quantities, compared to many contemporary 8-bit based CPUs. As instructions varied from one to six bytes, fetch and execution were made ] and decoupled into separate units (as it remains in today's x86 processors): The ''bus interface unit'' fed the instruction stream to the ''execution unit'' through a 6-byte prefetch queue (a form of loosely coupled ]), speeding up operations on ]s and ]s, while memory operations unfortunately became slower (four years later, this performance problem was fixed with the ] and ]). However, the full (instead of partial) 16-bit architecture with a full width ] meant that 16-bit arithmetic instructions could now be performed with a single ALU cycle (instead of two, via internal carry, as in the 8080 and 8085), speeding up such instructions considerably. Combined with ]s of operations versus ] types and ]s, as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below).

	{\| class="wikitable" style="text-align: center; width: 100px; height: 50px;"
	\|+ Execution times for typical instructions (in clock cycles)<ref>{{cite book\|title=] 5.0 Reference Manual\|year=1987\|publisher=Microsoft Corporation\| quote=Timings and encodings in this manual are used with permission of Intel and come from the following publications: Intel Corporation. iAPX 86, 88, 186 and 188 User's Manual, Programmer's Reference, Santa Clara, Calif. 1986.}} (Similarly for iAPX 286, 80386, 80387.)</ref>
	\|- style="vertical-align:bottom; border-bottom:3px double #999;"
	!align=left \| instruction
	!align=left \| register-register
	!align=left \| register immediate
	!align=left \| register-memory
	!align=left \| memory-register
	!align=left \| memory-immediate
	\|- style="vertical-align:top; border-bottom:1px solid #999;"
	\|mov \|\| 2 \|\| 4\|\| 8+EA \|\| 9+EA \|\| 10+EA
	\|- style="vertical-align:top; border-bottom:1px solid #999;"
	\|ALU \|\| 3 \|\|4\|\| 9+EA, \|\| 16+EA,\|\| 17+EA
	\|- style="vertical-align:top; border-bottom:1px solid #999;"
	\|jump \|\| colspan="5" \| ''register'' => 11 ; ''label'' => 15 ; ''condition,label'' => 16
	\|- style="vertical-align:top; border-bottom:1px solid #999;"
	\|integer multiply \|\| colspan="5" \| 70~160 (depending on operand ''data'' as well as size) ''including'' any EA
	\|- style="vertical-align:top; border-bottom:1px solid #999;"
	\|integer divide \|\| colspan="5" \| 80~190 (depending on operand ''data'' as well as size) ''including'' any EA
	\|}
	* EA = time to compute effective address, ranging from 5 to 12 cycles.
	* Timings are best case, depending on prefetch status, instruction alignment, and other factors.

	As can be seen from these tables, operations on registers and immediates were fast (between 2 and 4 cycles), while memory-operand instructions and jumps were quite slow; jumps took more cycles than on the simple ] and ], and the 8088 (used in the IBM PC) was additionally hampered by its narrower bus. The reasons why most memory related instructions were slow were threefold:

	* Loosely coupled fetch and execution units are efficient for instruction prefetch, but not for jumps and random data access (without special measures).
	* No dedicated address calculation adder was afforded; the microcode routines had to use the main ALU for this (although there was a dedicated ''segment'' + ''offset'' adder).
	* The address and data buses were ]ed, forcing a slightly longer (33~50%) bus cycle than in typical contemporary 8-bit processors.

	However, memory access performance was drastically enhanced with Intel's next generation chips. The ] and ] both had dedicated address calculation hardware, saving many cycles, and the 80286 also had separate (non-multiplexed) address and data buses.

	===Floating point===
	The 8086/8088 could be connected to a mathematical coprocessor to add hardware/microcode-based ] performance. The ] was the standard math coprocessor for the 8086 and 8088, operating on 80-bit numbers. Manufacturers like ] (8087-compatible) and ] (''non'' 8087-compatible) eventually came up with high performance floating point coprocessors that competed with the 8087 as well as with the subsequent, higher performing ].

	==Chip versions==
	The clock frequency was originally limited to 5 MHz (IBM PC used 4.77 MHz, 4/3 the standard NTSC ] frequency), but the last versions in ] were specified for 10 MHz. HMOS-III and ] versions were manufactured for a long time (at least a while into the 1990s) for ]s, although its successor, the ]/] (which includes some on-chip peripherals), has been more popular for embedded use.

	The 80C86, the CMOS version of the 8086, was used in the ], ], ], and finally the 1998-1999 ].

	===List of Intel 8086===
	{\| class="wikitable"
	\|-
	! Model Number
	! Frequency
	! Technology
	! Temperature Range
	! Date of Released
	! Price (USD){{ref\|quantity}}
	\|-
	\| 8086
	\| 5 MHz
	\| HMOS
	\| 0°C - 70°C<ref>8086 Available for industrial environment, Intel Preview Special Issue: 16-Bit Solutions, Intel Corporation, May/June 1980, page 29</ref>
	\| June 8, 1978<ref></ref>
	\| $86.65<ref>The 8086 Family: Concepts and realities, Intel Preview Special Issue: 16-Bit Solutons, Intel Corporation, May/June 1980, page 19</ref>
	\|-
	\| 8086-1
	\|
	\|
	\|
	\|
	\|
	\|-
	\| 8086-2
	\| 8 MHz
	\| HMOS II
	\| Commercial
	\| May/June 1980<ref>New 8086 family products boots processor performance by 50 percent, Intel Preview Special Issue: 16-Bit Solutions, Intel Corporation, May/June 1980, page 17</ref>
	\| $200<ref>New 8086 family products boots processor performance by 50 percent, Intel Preview Special Issue: 16-Bit Solutions, Intel Corporation, May/June 1980, page 17</ref>
	\|-
	\| I8086
	\|
	\|
	\| -40°C - +85°C<ref>8086 Available for industrial environment, Intel Preview Special Issue: 16-Bit Solutions, Intel Corporation, May/June 1980, page 29</ref>
	\| May/June 1980<ref>8086 Available for industrial environment, Intel Preview Special Issue: 16-Bit Solutions, Intel Corporation, May/June 1980, page 29</ref>
	\| $173.25<ref>8086 Available for industrial environment, Intel Preview Special Issue: 16-Bit Solutions, Intel Corporation, May/June 1980, page 29</ref>
	\|}

	# {{note\|quantity}} In quantity of 100

	===Derivatives and clones===
	]
	] M80C86A ]]]
	]
	Compatible—and, in many cases, enhanced—versions were manufactured by ], ]/], ], ], ], ], ], ]. For example, the ] and ] pair were hardware compatible with the 8088 and 8086 even though NEC made original Intel clones μPD8088D and μPD8086D, respectively, but incorporated the instruction set of the 80186 along with some (but not all) of the 80186 speed enhancements, providing a drop-in capability to upgrade both instruction set and processing speed without manufacturers having to modify their designs. Such relatively simple and low-power 8086-compatible processors in CMOS are still used in embedded systems.

	The electronics industry of the ] was able to replicate the 8086 through {{citation needed-span\|both ] and reverse engineering.\|date=October 2013}} The resulting chip, ], was binary and pin-compatible with the 8086.

	i8088 and i8086 were respectively the cores of the Soviet-made PC-compatible ] and ] desktops (EC1831 is the EC identification of IZOT 1037C and EC1832 is the EC identification of IZOT 1036C, developed and manufactured in Bulgaria). However, EC1832 computer (IZOT 1036C) had significant hardware differences from its authentic prototype, and the data/address bus circuitry was designed independently of Intel products.{{verify source\|date=July 2011}} EC1832 was the first PC compatible computer with dynamic bus sizing (US Pat. No 4,831,514). Later some of the ES1832 principles were adopted in PS/2 (US Pat. No 5,548,786) and some other machines (UK Patent Application, Publication No. GB-A-2211325, Published June 28, 1989).

	==Hardware modes==
	The 8086 and 8088 support two hardware modes: maximum mode and minimum mode. Maximum mode is for large applications such as multiprocessing and is also required to support the 8087 coprocessor. The mode is usually hardwired into the circuit and cannot be changed by software. Specifically, pin #33 (MN/{{overline\|MX}}) is either wired to voltage or to ground to determine the mode. Changing the state of pin #33 changes the function of certain other pins, most of which have to do with how the CPU handles the (local) bus. The IBM PC and PC/XT use an Intel 8088 running in maximum mode, which allows the CPU to work with an optional 8087 coprocessor installed in the math coprocessor socket on the PC or PC/XT mainboard. (The PC and PC/XT may require Max mode for other reasons, such as perhaps to support the DMA controller.)The working of Minimum mode configuration can describe in the terms of Timing Diagrams.

	MINIMUM MODE: In minimum mode 8086 bases system,the microprocessor 8086 is operated minimum mode by strapping its MN/MX pin to logic high i.e.+5V.minimum mode all control singnals are generated by the microprocessor 8086 itself.

	Components in minimum mode are latches,trans-receiver,clock generator,memory and I/O device.

	==Peripherals==
	* ]: direct memory access (DMA) controller
	* ]: USART
	* ]: programmable interval timer
	* ]: programmable peripheral interface
	* ]: programmable interrupt controller
	* ]: keyboard/display controller
	* ]/]: 8-bit latch
	* ]: clock generator
	* ]/]: bidirectional 8-bit driver
	* ]: bus controller
	* ]: bus arbiter

	==Microcomputers using the 8086==
	* The ] was one of the earliest ] designs in 1978 and used three 8086 chips (as CPU, graphics processor, and i/o processor), but never entered commercial production.
	* ] shipped ] based 8086 systems (SCP200B) as early as November 1979.
	* The Norwegian ] 2000, introduced in 1980.
	* One of the most influential microcomputers of all, the ], used the ], a version of the 8086 with an 8-bit ] (as mentioned above).
	* The first ] used an 8086 running at 7.14 MHz, (?) but was capable of running add-in cards designed for the 4.77 MHz ].
	* An 8 MHz 8086 was used in the ] (built by ]), an IBM PC-compatible desktop microcomputer. The M24 / PC 6300 has IBM PC/XT compatible 8-bit expansion slots, but some of them have a proprietary extension providing the full 16-bit data bus of the 8086 CPU (similar in concept to the 16-bit slots of the ], but different in the design details, and physically incompatible).
	* The ] models 25 and 30 were built with an 8 MHz 8086.
	* The Amstrad/Schneider ], ], ], ] and ] all used 8086 CPUs at 8 MHz.
	* The ].
	* The ] SL-series and RL machines used 9.47 MHz 8086 CPUs.
	* The ] word processing machine<ref name = "InfoWorld Aug 1982" >{{cite journal
	\| last = Zachmann \| first = Mark
	\| title = Flaws in IBM Personal Computer frustrate critic
	\| journal = InfoWorld \| volume = 4 \| issue = 33
	\| pages =57–58
	\| publisher = Popular Computing \| location = Palo Alto, CA
	\| date = August 23, 1982
	\| url = http://books.google.com/books?id=VDAEAAAAMBAJ&pg=PA57\| issn = 0199-6649
	\| quote = the IBM Displaywriter is noticeably more expensive than other industrial micros that use the 8086.
	}}</ref> and the Wang Professional Computer, manufactured by ], also used the 8086.
	* ] used original 8086 CPUs on equipment for ground-based maintenance of the ] until the end of the space shuttle program in 2011. This decision was made to prevent ] that might result from upgrading or from switching to imperfect clones.<ref>, May 12, 2002.</ref>
	* KAMAN Process and Area Radiation Monitors<ref>Kaman Tech. Manual</ref>

	==Notes==
	{{Reflist\|group=note\|liststyle=lower-roman}}

	==See also==
	* ]
	* ], for the iAPX name

	==References==
	{{Reflist\|colwidth=35em}}

	==External links==
	*
	*
	*
	*
	*
	* (] document)
	*
	*
	{{Intel processors\|discontinued}}

	{{Authority control}}

	]
	]<!--Note: NOT a typo for 8086, this is done for numberical ordering of categories-->

Revision as of 07:24, 24 November 2015