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| Also, there are no MPUs that have shipped with more than 2 simultaneous threads (POWER5 and Pentium 4). Other MPUs from Sun and Raza Microelectric use coarse grained multithreading. Since instructions cannot execute from multiple threads at the same time, it is not simultaneous. | Also, there are no MPUs that have shipped with more than 2 simultaneous threads (POWER5 and Pentium 4). Other MPUs from Sun and Raza Microelectric use coarse grained multithreading. Since instructions cannot execute from multiple threads at the same time, it is not simultaneous. | ||
| ==Montecito== | |||
| Montecito uses SMT: http://www.doc.ic.ac.uk/~phjk/AdvancedCompArchitecture/PastPapers/2003-2004-MEng3Test.pdf you can read at 1.b: ''"In a proposed simultaneous multi-threading (SMT, also known as hyperthreaded) Itanium 2 design, a single CPU core is extended with two program counters, and two register sets, so that it can execute two different threads at the same time. | |||
| Referring to Figure 1 (page 46), identify which parts of the design would have to be changed, and explain briefly what would have to be done."'' | Montecito uses SMT: http://www.doc.ic.ac.uk/~phjk/AdvancedCompArchitecture/PastPapers/2003-2004-MEng3Test.pdf you can read at 1.b: ''"In a proposed simultaneous multi-threading (SMT, also known as hyperthreaded) Itanium 2 design, a single CPU core is extended with two program counters, and two register sets, so that it can execute two different threads at the same time. Referring to Figure 1 (page 46), identify which parts of the design would have to be changed, and explain briefly what would have to be done."'' --] 07:53, 24 November 2006 (UTC) | ||
Revision as of 07:53, 24 November 2006
"In 2005, security concerns were made public by Colin Percival, Cache missing for fun and profit demonstrating that malicious threads can monitor the execution of other threads."
I think this is an interesting fact that User:62.15.117.39 brought up in this revision, so am putting it here. But I agree with User:69.134.163.109 that it's not necessarily a detail for an encyclopedia article. -- Furchild 22:11, Jun 26, 2005 (UTC)
Oh. Another link that is more informative: Hyper-Threading Considered Harmful. -- Furchild 22:59, Jun 26, 2005 (UTC)
NB: SMT can always lower performance by forcing a thread to share resources. Imagine the situation of a thread which requires all ROB entries for a modern MPU to execute without stalls, the minute SMT is turned on, it will begin stalling. SMT *usually* increases performance, but it is not guaranteed and can lower performance
Also, there are no MPUs that have shipped with more than 2 simultaneous threads (POWER5 and Pentium 4). Other MPUs from Sun and Raza Microelectric use coarse grained multithreading. Since instructions cannot execute from multiple threads at the same time, it is not simultaneous.
Montecito
Montecito uses SMT: http://www.doc.ic.ac.uk/~phjk/AdvancedCompArchitecture/PastPapers/2003-2004-MEng3Test.pdf you can read at 1.b: "In a proposed simultaneous multi-threading (SMT, also known as hyperthreaded) Itanium 2 design, a single CPU core is extended with two program counters, and two register sets, so that it can execute two different threads at the same time. Referring to Figure 1 (page 46), identify which parts of the design would have to be changed, and explain briefly what would have to be done." --134.155.99.41 07:53, 24 November 2006 (UTC)