The following pages link to SWAR
External toolsShowing 50 items.
View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)- Apollo Guidance Computer (links | edit)
- IAS machine (links | edit)
- Instructions per cycle (links | edit)
- Instruction pipelining (links | edit)
- Flynn's taxonomy (links | edit)
- Clock rate (links | edit)
- Instruction-level parallelism (links | edit)
- Power management (links | edit)
- Barrel shifter (links | edit)
- Simultaneous multithreading (links | edit)
- Speculative execution (links | edit)
- Memory-mapped I/O and port-mapped I/O (links | edit)
- Back-side bus (links | edit)
- Mobile processor (links | edit)
- Coprocessor (links | edit)
- Index register (links | edit)
- Hazard (computer architecture) (links | edit)
- Classic RISC pipeline (links | edit)
- Branch predictor (links | edit)
- Execution (computing) (links | edit)
- Adder (electronics) (links | edit)
- Register renaming (links | edit)
- Prefetch input queue (links | edit)
- Von Neumann architecture (links | edit)
- Processor register (links | edit)
- DEC PRISM (links | edit)
- 4-bit computing (links | edit)
- Translation lookaside buffer (links | edit)
- Instruction cycle (links | edit)
- NX bit (links | edit)
- Explicitly parallel instruction computing (links | edit)
- Addressing mode (links | edit)
- CPU cache (links | edit)
- CORDIC (links | edit)
- Temporal multithreading (links | edit)
- 36-bit computing (links | edit)
- Multiple instruction, single data (links | edit)
- Out-of-order execution (links | edit)
- Single instruction, single data (links | edit)
- Memory buffer register (links | edit)
- General-purpose computing on graphics processing units (links | edit)
- Orthogonal instruction set (links | edit)
- Dataflow architecture (links | edit)
- Microarchitecture (links | edit)
- Network processor (links | edit)
- Physics processing unit (links | edit)
- Word (computer architecture) (links | edit)
- Clipper architecture (links | edit)
- Register file (links | edit)
- Ferranti Mercury (links | edit)