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Revision as of 03:27, 11 September 2008 by Ramu50 (talk | contribs)(diff) ← Previous revision | Latest revision (diff) | Newer revision → (diff)| CPU technologies | |
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| Architecture | ISA : CISC · EPIC · OISC · RISC · VLIW · ZISC · CISC-RISC (x86) · Harvard architecture · Von Neumann architecture |
| Parallelism | ILP (Superscalar) · Instruction pipelining (In-Order & Out-of-Order execution) · Register renaming (TLB) ·
Multithreading · Simultaneous multithreading (Hyperthreading · Superthreading) · Multiprocessing Logic (Bitwise operation · Speculative execution) |
| Components | Template:Navbox subgroup |
| Power management | Advanced Power Management · APCI (states) · DPMS (VESA) · Dynamic frequency scaling · Dynamic voltage scaling · Clock gating |
| Diode (education) --- cf Electrochemistry / REDOX Cathode and Anode | |